vhdl sequential signal assignment

In VHDL -93, any signal assignment statement may have an optional label:

VHDL Logical Operators and Signal Assignments for Combinational Logic

In this post, we discuss the VHDL logical operators, when-else statements , with-select statements and instantiation . These basic techniques allow us to model simple digital circuits.

In a previous post in this series, we looked at the way we use the VHDL entity, architecture and library keywords. These are important concepts which provide structure to our code and allow us to define the inputs and outputs of a component.

However, we can't do anything more than define inputs and outputs using this technique. In order to model digital circuits in VHDL, we need to take a closer look at the syntax of the language.

There are two main classes of digital circuit we can model in VHDL – combinational and sequential .

Combinational logic is the simplest of the two, consisting primarily of basic logic gates , such as ANDs, ORs and NOTs. When the circuit input changes, the output changes almost immediately (there is a small delay as signals propagate through the circuit).

Sequential circuits use a clock and require storage elements such as flip flops . As a result, changes in the output are synchronised to the circuit clock and are not immediate. We talk more specifically about modelling combinational logic in this post, whilst sequential logic is discussed in the next post.

Combinational Logic

The simplest elements to model in VHDL are the basic logic gates – AND, OR, NOR, NAND, NOT and XOR.

Each of these type of gates has a corresponding operator which implements their functionality. Collectively, these are known as logical operators in VHDL.

To demonstrate this concept, let us consider a simple two input AND gate such as that shown below.

The VHDL code shown below uses one of the logical operators to implement this basic circuit.

Although this code is simple, there are a couple of important concepts to consider. The first of these is the VHDL assignment operator (<=) which must be used for all signals. This is roughly equivalent to the = operator in most other programming languages.

In addition to signals, we can also define variables which we use inside of processes. In this case, we would have to use a different assignment operator (:=).

It is not important to understand variables in any detail to model combinational logic but we talk about them in the post on the VHDL process block .

The type of signal used is another important consideration. We talked about the most basic and common VHDL data types in a previous post.

As they represent some quantity or number, types such as real, time or integer are known as scalar types. We can't use the VHDL logical operators with these types and we most commonly use them with std_logic or std_logic_vectors.

Despite these considerations, this code example demonstrates how simple it is to model basic logic gates.

We can change the functionality of this circuit by replacing the AND operator with one of the other VHDL logical operators.

As an example, the VHDL code below models a three input XOR gate.

The NOT operator is slightly different to the other VHDL logical operators as it only has one input. The code snippet below shows the basic syntax for a NOT gate.

• Mixing VHDL Logical Operators

Combinational logic circuits almost always feature more than one type of gate. As a result of this, VHDL allows us to mix logical operators in order to create models of more complex circuits.

To demonstrate this concept, let’s consider a circuit featuring an AND gate and an OR gate. The circuit diagram below shows this circuit.

The code below shows the implementation of this circuit using VHDL.

This code should be easy to understand as it makes use of the logical operators we have already talked about. However, it is important to use brackets when modelling circuits with multiple logic gates, as shown in the above example. Not only does this ensure that the design works as intended, it also makes the intention of the code easier to understand.

• Reduction Functions

We can also use the logical operators on vector types in order to reduce them to a single bit. This is a useful feature as we can determine when all the bits in a vector are either 1 or 0.

We commonly do this for counters where we may want to know when the count reaches its maximum or minimum value.

The logical reduction functions were only introduced in VHDL-2008. Therefore, we can not use the logical operators to reduce vector types to a single bit when working with earlier standards.

The code snippet below shows the most common use cases for the VHDL reduction functions.

Mulitplexors in VHDL

In addition to logic gates, we often use multiplexors (mux for short) in combinational digital circuits. In VHDL, there are two different concurrent statements which we can use to model a mux.

The VHDL with select statement, also commonly referred to as selected signal assignment, is one of these constructs.

The other method we can use to concurrently model a mux is the VHDL when else statement.

In addition to this, we can also use a case statement to model a mux in VHDL . However, we talk about this in more detail in a later post as this method also requires us to have an understanding of the VHDL process block .

Let's look at the VHDL concurrent statements we can use to model a mux in more detail.

VHDL With Select Statement

When we use the with select statement in a VHDL design, we can assign different values to a signal based on the value of some other signal in our design.

The with select statement is probably the most intuitive way of modelling a mux in VHDL.

The code snippet below shows the basic syntax for the with select statement in VHDL.

When we use the VHDL with select statement, the <mux_out> field is assigned data based on the value of the <address> field.

When the <address> field is equal to <address1> then the <mux_out> signal is assigned to <a>, for example.

We use the the others clause at the end of the statement to capture instance when the address is a value other than those explicitly listed.

We can exclude the others clause if we explicitly list all of the possible input combinations.

• With Select Mux Example

Let’s consider a simple four to one multiplexer to give a practical example of the with select statement. The output Q is set to one of the four inputs (A,B, C or D) depending on the value of the addr input signal.

The circuit diagram below shows this circuit.

This circuit is simple to implement using the VHDL with select statement, as shown in the code snippet below.

VHDL When Else Statements

We use the when statement in VHDL to assign different values to a signal based on boolean expressions .

In this case, we actually write a different expression for each of the values which could be assigned to a signal. When one of these conditions evaluates as true, the signal is assigned the value associated with this condition.

The code snippet below shows the basic syntax for the VHDL when else statement.

When we use the when else statement in VHDL, the boolean expression is written after the when keyword. If this condition evaluates as true, then the <mux_out> field is assigned to the value stated before the relevant when keyword.

For example, if the <address> field in the above example is equal to <address1> then the value of <a> is assigned to <mux_out>.

When this condition evaluates as false, the next condition in the sequence is evaluated.

We use the else keyword to separate the different conditions and assignments in our code.

The final else statement captures the instances when the address is a value other than those explicitly listed. We only use this if we haven't explicitly listed all possible combinations of the <address> field.

• When Else Mux Example

Let’s consider the simple four to one multiplexer again in order to give a practical example of the when else statement in VHDL. The output Q is set to one of the four inputs (A,B, C or D) based on the value of the addr signal. This is exactly the same as the previous example we used for the with select statement.

The VHDL code shown below implements this circuit using the when else statement.

• Comparison of Mux Modelling Techniques in VHDL

When we write VHDL code, the with select and when else statements perform the same function. In addition, we will get the same synthesis results from both statements in almost all cases.

In a purely technical sense, there is no major advantage to using one over the other. The choice of which one to use is often a purely stylistic choice.

When we use the with select statement, we can only use a single signal to determine which data will get assigned.

This is in contrast to the when else statements which can also include logical descriptors.

This means we can often write more succinct VHDL code by using the when else statement. This is especially true when we need to use a logic circuit to drive the address bits.

Let's consider the circuit shown below as an example.

To model this using a using a with select statement in VHDL, we would need to write code which specifically models the AND gate.

We must then include the output of this code in the with select statement which models the multiplexer.

The code snippet below shows this implementation.

Although this code would function as needed, using a when else statement would give us more succinct code. Whilst this will have no impact on the way the device works, it is good practice to write clear code. This help to make the design more maintainable for anyone who has to modify it in the future.

The VHDL code snippet below shows the same circuit implemented with a when else statement.

Instantiating Components in VHDL

Up until this point, we have shown how we can use the VHDL language to describe the behavior of circuits.

However, we can also connect a number of previously defined VHDL entity architecture pairs in order to build a more complex circuit.

This is similar to connecting electronic components in a physical circuit.

There are two methods we can use for this in VHDL – component instantiation and direct entity instantiation .

• VHDL Component Instantiation

When using component instantiation in VHDL, we must define a component before it is used.

We can either do this before the main code, in the same way we would declare a signal, or in a separate package.

VHDL packages are similar to headers or libraries in other programming languages and we discuss these in a later post.

When writing VHDL, we declare a component using the syntax shown below. The component name and the ports must match the names in the original entity.

After declaring our component, we can instantiate it within an architecture using the syntax shown below. The <instance_name> must be unique for every instantiation within an architecture.

In VHDL, we use a port map to connect the ports of our component to signals in our architecture.

The signals which we use in our VHDL port map, such as <signal_name1> in the example above, must be declared before they can be used.

As VHDL is a strongly typed language, the signals we use in the port map must also match the type of the port they connect to.

When we write VHDL code, we may also wish to leave some ports unconnected.

For example, we may have a component which models the behaviour of a JK flip flop . However, we only need to use the inverted output in our design meaning. Therefore, we do not want to connect the non-inverted output to a signal in our architecture.

We can use the open keyword to indicate that we don't make a connection to one of the ports.

However, we can only use the open VHDL keyword for outputs.

If we attempt to leave inputs to our components open, our VHDL compiler will raise an error.

• VHDL Direct Entity Instantiation

The second instantiation technique is known as direct entity instantiation.

Using this method we can directly connect the entity in a new design without declaring a component first.

The code snippet below shows how we use direct entity instantiation in VHDL.

As with the component instantiation technique, <instance_name> must be unique for each instantiation in an architecture.

There are two extra requirements for this type of instantiation. We must explicitly state the name of both the library and the architecture which we want to use. This is shown in the example above by the <library_name> and <architecture_name> labels.

Once the component is instantiated within a VHDL architecture, we use a port map to connect signals to the ports. We use the VHDL port map in the same way for both direct entity and component instantiation.

Which types can not be used with the VHDL logical operators?

Scalar types such as integer and real.

Write the code for a 4 input NAND gate

We can use two different types of statement to model multiplexors in VHDL, what are they?

The with select statement and the when else statement

Write the code for an 8 input multiplexor using both types of statement

Write the code to instantiate a two input AND component using both direct entity and component instantiation. Assume that the AND gate is compiled in the work library and the architecture is named rtl.

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Save my name, email, and website in this browser for the next time I comment.

Table of Contents

Sign up free for exclusive content.

Don't Miss Out

We are about to launch exclusive video content. Sign up to hear about it first.

Sequential Signal Assignment

Reference manual.

• Section 8.3

Rules and Examples

A sequential signal assignment takes effect only when the process suspends. If there is more than one assignment to the same signal before suspension, the last one executed takes effect:

An equivalent process:

In this architecture, the signals Y and Z will both get the same value (2*A + B) because even though two assignments to the signal M are executed, the first will always be superseded by the second

If a signal which has assignments to it within a process is also in the sensitivity list, it may cause the process to be reactivated.

A sequential signal assignment may have a delay:

The rules about what happens when a delayed signal assignment is subsequently overridden are complex: see the reference manual.

A delayed sequential signal assignment does not suspend the process or procedure for the time specified. The assignment is scheduled to occur after the specified time, and any further sequential statements are executed immediately.

Any signal assignment statement may have an optional label:

A delayed signal assignment with inertial delay may be explicitly preceded by the keyword inertial . It may also have a reject time specified. This is the minimum “pulse width” to be propagated, if different from the inertial delay:

Synthesis Issues

Sequential signal assignments are generally synthesizable, providing they use types and operators acceptable to the synthesis tool. Delays are usually ignored.

All signals with assignments to them within a “clocked process” will become the outputs of registers in the synthesized design.

Signals driven by a “combinational process” will be inferred as the outputs of combinational logic but a signal which is assigned only under certain conditions may infer a latch. Assignment to ‘Z’ will normally generate tri-state drivers. assignment to ‘X’ may not be supported.

VHDL (Part 2)

• First Online: 20 March 2019

Cite this chapter

• Brock J. LaMeres 2  

120k Accesses

In Chap. 5 VHDL was presented as a way to describe the behavior of concurrent systems. The modeling techniques presented were appropriate for combinational logic because these types of circuits have outputs dependent only on the current values of their inputs. This means a model that continuously performs signal assignments provides an accurate model of this circuit behavior. In Chap. 7 sequential logic storage devices were presented that did not continuously update their outputs based on the instantaneous values of their inputs. Instead, sequential storage devices only update their outputs based upon an event, most often the edge of a clock signal. The modeling techniques presented in Chap. 5 are unable to accurately describe this type of behavior. In this chapter we describe the VHDL constructs to model signal assignments that are triggered by an event in order to accurately model sequential logic. We can then use these techniques to describe more complex sequential logic circuits such as finite state machines and register transfer level systems. This chapter will also present how to create test benches and look at commonly used packages that increase the capability and accuracy with which VHDL can model modern systems. The goal of this chapter is to give an understanding of the full capability of hardware description languages.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

• Available as PDF
• Read on any device
• Instant download
• Own it forever
• Available as EPUB and PDF
• Compact, lightweight edition
• Dispatched in 3 to 5 business days
• Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Author information

Authors and affiliations.

Department of Electrical & Computer Engineering, Montana State University, Bozeman, MT, USA

Brock J. LaMeres

You can also search for this author in PubMed   Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Switzerland AG

About this chapter

LaMeres, B.J. (2019). VHDL (Part 2). In: Introduction to Logic Circuits & Logic Design with VHDL . Springer, Cham. https://doi.org/10.1007/978-3-030-12489-2_8

Download citation

DOI : https://doi.org/10.1007/978-3-030-12489-2_8

Published : 20 March 2019

Publisher Name : Springer, Cham

Print ISBN : 978-3-030-12488-5

Online ISBN : 978-3-030-12489-2

eBook Packages : Engineering Engineering (R0)

Share this chapter

Anyone you share the following link with will be able to read this content:

Sorry, a shareable link is not currently available for this article.

Provided by the Springer Nature SharedIt content-sharing initiative

• Publish with us

Policies and ethics

• Find a journal
• Track your research

A signal assignment statement modifies the target signal

Description:

A Signal assignment statement can appear inside a process (sequential statement) or directly in an architecture (concurrent statement). The target signal can be either a name (simple, selected, indexed, or slice) or an aggregate .

A signal assignment with no delay (or zero delay) will cause an event after delta delay, which means that the event happens only when all of the currently active processes have finished executing (i.e. after one simulation cycle).

The default delay mode ( inertial ) means that pulses shorter than the delay (or the reject period if specified) are ignored. Transport means that the assignment acts as a pure delay line.

VHDL'93 defines the keyword unaffected which indicates a choice where the signal is not given a new assignment. This is roughly equivalent to the use of the null statement within case (see Examples).

• Delays are usually ignored by synthesis tool.

Aggregate , Concurrent statement , Sequential statement , Signal , Variable assignment

• Top Courses
• Online Degrees
• Find your New Career
• Join for Free

Fundamentals of Digital Design for VLSI Chip Design

This course is part of Chip based VLSI design for Industrial Applications Specialization

Taught in English

Instructor: Subject Matter Expert

Financial aid available

Recommended experience

Intermediate level

Professionals in Semiconductor Design Department, VLSI Engineering Department, Electronics Engineering Department, IC Design Department

Skills you'll gain

• Combinational and Sequential Circuits
• FPGA Architecture and Applications
• VHDL Programming
• Digital Circuit Design
• Memory Types and Programmable Logic Devices (PLDs

Details to know

Add to your LinkedIn profile

4 assignments

See how employees at top companies are mastering in-demand skills

Build your subject-matter expertise

• Learn new concepts from industry experts
• Gain a foundational understanding of a subject or tool
• Develop job-relevant skills with hands-on projects
• Earn a shareable career certificate

Earn a career certificate

Add this credential to your LinkedIn profile, resume, or CV

Share it on social media and in your performance review

There are 4 modules in this course

This comprehensive learning module delves into Boolean algebra and its applications in digital circuit design, covering fundamental concepts like Boolean variables, logic gates, and their relationship with digital logic circuits. Participants explore Boolean expressions, simplification techniques, and consensus theorems, including the advanced Quine McCluskey method.

The module also addresses combinational circuits, detailing the design and functionality of adders, subtractors, parity circuits, and multipliers. Encoding complexities are navigated with insights into encoders, decoders, multiplexers, and demultiplexers. Binary shifting operations, emphasizing logical and arithmetic shifting with multiplexers for efficient design, are covered. Moving forward, the module provides an in-depth exploration of sequential circuits, including latch and flip-flop circuits like SR latch, JK flip-flop, and more. Hazards in digital circuits, along with registers, bidirectional shift registers, and various counters, are thoroughly explained. The exploration concludes with Mealy and Moore state sequential circuits. Additionally, participants gain a comprehensive understanding of memory systems, programmable logic devices, and VLSI physical design considerations. The module covers SRAM and DRAM, tri-state digital buffers, Read-Only Memory (ROM), and Programmable Logic Devices (PLD) such as PROM, PLA, and PAL. Architecture and implementation of Complex Programmable Logic Devices (CPLD) and Field-Programmable Gate Arrays (FPGA) are discussed, along with the VLSI design cycle and design styles for CPLD, SPLD, and FPGA. By the end of this course, you will be able to:  Understand the distinctions between analog and digital signals and the transformative benefits of digitization.  Comprehend various number systems, Boolean algebra, and its application to logic gates.  Master Boolean expression manipulation, canonical forms, and simplification techniques.  Proficiently handle SOP and POS expressions, recognizing relationships between minterms and maxterms.  Recognize the universality of NAND and NOR gates, implementing functions using De Morgan's Law.  Master Karnaugh map techniques, including advanced methods and handling don't care conditions.  Gain a comprehensive understanding of combinational circuits, covering principles and applications.  Understand binary addition principles and design various adder circuits, including 4-bit ripple carry adders.  Explore advanced adder designs for arithmetic operations.  Proficiently design binary subtractors, analyze overflow/underflow scenarios, and understand signed number representation.  Understand parity generation, detection, and various methods of binary multiplication.  Master the design and application of various multipliers, incorporating the Booth algorithm.  Understand applications of comparators, encoders, and decoders in digital systems.  Proficiently use multiplexers and demultiplexers in digital circuit design, recognizing their role as function generators.  Understand binary shifting operations, designing logical shifters, and principles of arithmetic and barrel shifting.  Grasp foundational principles of sequential circuits, focusing on storage elements and designing an SR latch.  Understand the operation of JK flip-flops, addressing race around conditions, and design master-slave JK flip-flops and Gated SR latches.  Gain proficiency in designing and analyzing various types of counters in sequential circuits.  Understand principles and design techniques for Mealy and Moore state sequential circuits.  Grasp fundamental principles of memory, differentiating internal structures between SRAM and DRAM, and gain practical skills in addressing memory, controlling tri-state digital buffers, and understanding ROM, PLD, and various PLDs.

Digital Fundamentals

This comprehensive learning module provides a detailed exploration of Boolean algebra and its practical applications in digital circuit design. Participants will delve into fundamental concepts such as Boolean variables, logic gates, and the relationship between Boolean algebra and digital logic circuits. The module progresses to cover Boolean expressions, simplification techniques, and the derivation of consensus theorems. Practical aspects, including the implementation of Boolean functions using universal gates and the use of Karnaugh maps for simplification, are thoroughly examined. The module also introduces the Quine McCluskey method as an advanced tool for Boolean expression simplification.

What's included

45 videos 3 readings 1 assignment

45 videos • Total 333 minutes

• About the Specialization • 3 minutes • Preview module
• About the Course • 5 minutes
• Need for Digital Logic Design • 7 minutes
• Introduction to Different Number System and their Conversions - Part 1 • 4 minutes
• Introduction to Different Number System and their Conversions - Part 2 • 4 minutes
• Introduction to Different Number System and their Conversions - Part 3 • 7 minutes
• Introduction to Different Number System and their Conversions - Part 4 • 3 minutes
• Introduction to Different Number System and their Conversions - Part 5 • 15 minutes
• Introduction to Various Codes in Digital System - Part 1 • 8 minutes
• Introduction to Various Codes in Digital System - Part 2 • 6 minutes
• Introduction to Various Codes in Digital System - Part 3 • 10 minutes
• Introduction to Boolean Algebra and Boolean Theorems - Part 1 • 5 minutes
• Introduction to Boolean Algebra and Boolean Theorems - Part 2 • 5 minutes
• Introduction to Boolean Algebra and Boolean Theorems - Part 3 • 7 minutes
• Minimization of Boolean Expressions by using Theorems - Part 1 • 8 minutes
• Minimization of Boolean Expressions by using Theorems - Part 2 • 6 minutes
• Minimization of Boolean Expressions by using Theorems - Part 3 • 10 minutes
• Minimization of Boolean Expressions by using Theorems - Part 4 • 6 minutes
• Minimization of Boolean Expressions by using Theorems - Part 5 • 10 minutes
• Canonical Forms in Digital Logic - SOP Part 1 • 6 minutes
• Canonical Forms in Digital Logic - SOP Part 2 • 8 minutes
• Canonical Forms in Digital Logic - POS Part 1 • 5 minutes
• Canonical Forms in Digital Logic - POS Part 2 • 7 minutes
• Implementation of Boolean Functions with NAND and NOR Gates - Part 1 • 8 minutes
• Implementation of Boolean Functions with NAND and NOR Gates - Part 2 • 10 minutes
• Implementation of Boolean Functions with NAND and NOR Gates - Part 3 • 2 minutes
• Implementation of Boolean Functions with NAND and NOR Gates - Part 4 • 6 minutes
• Implementation of Boolean Functions with NAND and NOR Gates - Part 5 • 10 minutes
• Introduction to Karnaugh Map • 8 minutes
• 2 and 3 Variable K-Map Simplification with Examples - Part 1 • 6 minutes
• 2 and 3 Variable K-Map Simplification with Examples - Part 2 • 9 minutes
• 2 and 3 Variable K-Map Simplification with Examples - Part 3 • 10 minutes
• 2 and 3 Variable K-Map Simplification with Examples - Part 4 • 7 minutes
• 2 and 3 Variable K-Map Simplification with Examples - Part 5 • 4 minutes
• 2 and 3 Variable K-Map Simplification with Examples - Part 6 • 6 minutes
• 4 Variable K-Map Simplification with Examples - Part 1 • 8 minutes
• 4 Variable K-Map Simplification with Examples - Part 2 • 8 minutes
• 4 Variable K-Map Simplification with Examples - Part 3 • 8 minutes
• K-Map Simplification for POS Expressions - Part 1 • 6 minutes
• K-Map Simplification for POS Expressions - Part 2 • 7 minutes
• K-Map Simplification for POS Expressions - Part 3 • 8 minutes
• Quine-McCluskey Method to Simplify Digital Logic - Part 1 • 5 minutes
• Quine-McCluskey Method to Simplify Digital Logic - Part 2 • 7 minutes
• Quine-McCluskey Method to Simplify Digital Logic - Part 3 • 5 minutes
• Quine-McCluskey Method to Simplify Digital Logic - Part 4 • 7 minutes

3 readings • Total 30 minutes

• Specialization Reading • 10 minutes
• Course Reading • 10 minutes
• Course Glossary • 10 minutes

1 assignment • Total 30 minutes

• Assignment on Digital Fundamentals • 30 minutes

Combinational Logic Design

This comprehensive module delves into the intricate world of combinational circuits and arithmetic operations in digital systems. Participants will explore the design and functionality of various circuits, including adders, subtractors, parity circuits, and multipliers. The module navigates through the complexities of encoding and decoding, introducing different types of encoders, decoders, multiplexers, and demultiplexers. Additionally, the module covers binary shifting operations, including logical and arithmetic shifting, utilizing multiplexers for efficient design.

35 videos 1 assignment

35 videos • Total 225 minutes

• Design of Binary Adder Part-1 • 4 minutes • Preview module
• Design of Binary Adder Part-2 • 9 minutes
• Design of Binary Adder Part-3 • 12 minutes
• Design of Multibit Adder Part-1 • 6 minutes
• Design of Multibit Adder Part-2 • 6 minutes
• Design of Binary Subtractor Part-1 • 4 minutes
• Design of Binary Subtractor Part-2 • 2 minutes
• Design of Binary Subtractor Part-3 • 10 minutes
• Design of Binary Subtractor Part-4 • 7 minutes
• Design of Parity Circuits • 6 minutes
• Design of Unsigned Multiplier Part-1 • 8 minutes
• Design of Unsigned Multiplier Part-2 • 5 minutes
• Design of Signed Multiplier Part-1 • 8 minutes
• Design of Signed Multiplier Part-2 • 7 minutes
• Design of Signed Multiplier Part-3 • 5 minutes
• Design of Signed Multiplier Part-4 • 7 minutes
• Design of Signed Multiplier Part-5 • 4 minutes
• Design of Magnitude Comparator Part-1 • 5 minutes
• Design of Magnitude Comparator Part-2 • 8 minutes
• Design of Magnitude Comparator Part-3 • 3 minutes
• Design of Encoder Part-1 • 8 minutes
• Design of Encoder Part-2 • 2 minutes
• Design of Decoder Part-1 • 4 minutes
• Design of Decoder Part-2 • 9 minutes
• Design of Decoder Part-3 • 4 minutes
• Design of Multiplexer Part-1 • 6 minutes
• Design of Multiplexer Part-2 • 2 minutes
• Design of Multiplexer Part-3 • 7 minutes
• Design of Demultiplexer Part-1 • 9 minutes
• Design of Demultiplexer Part-2 • 6 minutes
• Design of Shifters 1 Part-1 • 5 minutes
• Design of Shifters 1 Part-2 • 4 minutes
• Design of Shifters 1 Part-3 • 5 minutes
• Design of Shifters 2 Part-1 • 6 minutes
• Design of Shifters 2 Part-2 • 7 minutes
• Assessment on Combinational Logic Design • 30 minutes

Sequential Logic Design

This comprehensive module provides an in-depth exploration of sequential circuits, covering the fundamental concepts, storage elements, and various types of flip-flops. Participants will gain insights into the design and operation of latch and flip-flop circuits, including SR latch, JK flip-flop, master-slave JK flip-flop, Gated SR latch, D latch, and D flip-flop. The module delves into hazards in digital circuits and explains the characteristics and applications of sequential circuits. Furthermore, the structure, operation, and types of registers are examined, alongside bidirectional shift registers. The module concludes with an extensive coverage of counters, including ring counters, Johnson counters, asynchronous up/down counters, synchronous up/down counters, and mod-n synchronous counters. The concepts of Mealy and Moore state sequential circuits are introduced, including the design of state diagrams, equivalent state tables, and reduction techniques.

24 videos 1 assignment

24 videos • Total 167 minutes

• Design of Sequential Circuits: SR Latch and Flip Flop - Part 1 • 4 minutes • Preview module
• Design of Sequential Circuits: SR Latch and Flip Flop - Part 2 • 9 minutes
• Design of Sequential Circuits: JK Flip Flop • 9 minutes
• Design of Sequential Circuits: D & T Latches and Flip Flops - Part 1 • 7 minutes
• Design of Sequential Circuits: D & T Latches and Flip Flops - Part 2 • 7 minutes
• Design of Sequential Circuits: Registers - Part 1 • 2 minutes
• Design of Sequential Circuits: Registers - Part 2 • 4 minutes
• Design of Sequential Circuits: Registers - Part 3 • 11 minutes
• Design of Sequential Circuits: Asynchronous Counters - Part 1 • 6 minutes
• Design of Sequential Circuits: Asynchronous Counters - Part 2 • 8 minutes
• Design of Sequential Circuits: Synchronous Counters - Part 1 • 8 minutes
• Design of Sequential Circuits: Synchronous Counters - Part 2 • 5 minutes
• Design of Sequential Circuits: Synchronous Counters - Part 3 • 8 minutes
• Design of Sequential Circuits: Synchronous Counters - Part 4 • 9 minutes
• Design of Sequential Circuits: Synchronous Counters - Part 5 • 4 minutes
• Design of Sequential Circuits: Synchronous Counters - Part 6 • 7 minutes
• Finite State Machines - Mealy State Sequential circuits - Part 1 • 5 minutes
• Finite State Machines - Mealy State Sequential circuits - Part 2 • 6 minutes
• Finite State Machines - Mealy State Sequential circuits - Part 3 • 5 minutes
• Finite State Machines - Mealy State Sequential circuits - Part 4 • 8 minutes
• Finite State Machines - Moore State Sequential circuits - Part 1 • 5 minutes
• Finite State Machines - Moore State Sequential circuits - Part 2 • 6 minutes
• Finite State Machines - Moore State Sequential circuits - Part 3 • 5 minutes
• Finite State Machines - Moore State Sequential circuits - Part 4 • 8 minutes
• Assessment on Sequential Logic Design • 30 minutes

Programmable Logic Devices

This module provides a comprehensive understanding of memory systems and programmable logic devices, along with insights into physical design considerations in VLSI. Participants will explore various types of memories, including SRAM and DRAM, examining their internal structures and addressing mechanisms. The module covers tri-state digital buffers, Read-Only Memory (ROM), Programmable Logic Devices (PLD) such as PROM, PLA, and PAL. Additionally, the architecture and implementation of Complex Programmable Logic Devices (CPLD) and Field-Programmable Gate Arrays (FPGA) are discussed. The module delves into the VLSI design cycle, hierarchical design, routing, compaction, extraction, and verification. Various VLSI design styles are explored, and the design processes for CPLD, SPLD, and FPGA are elucidated.

27 videos 1 assignment

27 videos • Total 180 minutes

• Memory and Its Types - Part 1 • 6 minutes • Preview module
• Memory and Its Types - Part 2 • 6 minutes
• Addressing of Memory - Part 1 • 8 minutes
• Addressing of Memory - Part 2 • 10 minutes
• Digital Design Using PROM - Part 1 • 6 minutes
• Digital Design Using PROM - Part 2 • 4 minutes
• Digital Design Using PLA - Part 1 • 7 minutes
• Digital Design Using PLA - Part 2 • 5 minutes
• Digital Design Using PLA - Part 3 • 3 minutes
• Digital Design Using PLA - Part 4 • 5 minutes
• Digital Design Using PLA - Part 5 • 6 minutes
• Digital Design Using PAL - Part 1 • 3 minutes
• Digital Design Using PAL - Part 2 • 7 minutes
• Digital Design Using PAL - Part 3 • 5 minutes
• Digital Design Using PAL - Part 4 • 5 minutes
• Digital Design Using PAL - Part 5 • 7 minutes
• Introduction to CPLD and FPGA 1 - Part 1 • 6 minutes
• Introduction to CPLD and FPGA 1 - Part 2 • 6 minutes
• Introduction to CPLD and FPGA 2 - Part 1 • 5 minutes
• Introduction to CPLD and FPGA 2 - Part 2 • 9 minutes
• VLSI Design Flow 1 - Part 1 • 3 minutes
• VLSI Design Flow 1 - Part 2 • 9 minutes
• VLSI Design Flow 1 - Part 3 • 7 minutes
• VLSI Design Flow 2 - Part 1 • 8 minutes
• VLSI Design Flow 2 - Part 2 • 8 minutes
• VLSI Design Flow 3 - Part 1 • 8 minutes
• VLSI Design Flow 3 - Part 2 • 6 minutes
• Assessment on Programmable Logic Devices • 30 minutes

Larsen & Toubro popularly known as L&T is an Indian Multinational conglomerate. L&T has over 8 decades of expertise in executing some of the most complex projects including the World's tallest statue - the Statue of Unity. L&T has a wide portfolio that includes engineering, construction, manufacturing, realty, ship building, defense, aerospace, IT & financial services. L&T EduTech is a e learning platform within the L&T Group, that offers courses that are curated & delivered by industry experts. In the world of engineering and technology, change and advancements are happening at the speed of light. Academia needs to keep pace with this change and career professionals need to adapt. This is the need gap L&T EduTech will fill. The vision for L&T EduTech is to be the bridge between academia and industry, between career professionals and ever-changing technology. L&T EduTech firmly believes that, only when these need gaps are filled, will we have truly empowered and knowledgeable workforce that will lead India in the future.

Recommended if you're interested in Electrical Engineering

L&T EduTech

VLSI Chip Design and Simulation with Electric VLSI EDA Tool

Design of Digital Circuits with VHDL Programming

FPGA Architecture Based System for Industrial Application

Why people choose coursera for their career.

Open new doors with Coursera Plus

Unlimited access to 7,000+ world-class courses, hands-on projects, and job-ready certificate programs - all included in your subscription

Advance your career with an online degree

Earn a degree from world-class universities - 100% online

Join over 3,400 global companies that choose Coursera for Business

Upskill your employees to excel in the digital economy

Frequently asked questions

When will i have access to the lectures and assignments.

Access to lectures and assignments depends on your type of enrollment. If you take a course in audit mode, you will be able to see most course materials for free. To access graded assignments and to earn a Certificate, you will need to purchase the Certificate experience, during or after your audit. If you don't see the audit option:

The course may not offer an audit option. You can try a Free Trial instead, or apply for Financial Aid.

The course may offer 'Full Course, No Certificate' instead. This option lets you see all course materials, submit required assessments, and get a final grade. This also means that you will not be able to purchase a Certificate experience.

What will I get if I subscribe to this Specialization?

When you enroll in the course, you get access to all of the courses in the Specialization, and you earn a certificate when you complete the work. Your electronic Certificate will be added to your Accomplishments page - from there, you can print your Certificate or add it to your LinkedIn profile. If you only want to read and view the course content, you can audit the course for free.

What is the refund policy?

If you subscribed, you get a 7-day free trial during which you can cancel at no penalty. After that, we don’t give refunds, but you can cancel your subscription at any time. See our full refund policy Opens in a new tab .

Is financial aid available?

Yes. In select learning programs, you can apply for financial aid or a scholarship if you can’t afford the enrollment fee. If fin aid or scholarship is available for your learning program selection, you’ll find a link to apply on the description page.

More questions

• StudentInfo

Academic Calendar

• > Catalogs
• > Courses
• > Electrical and Computer Engineering

Keys and Symbols Reference

Electrical and Computer Engineering (ECE)

Insight into electrical and computer engineering is gained through videos and the use of computer software to learn basic problem-solving skills.  

Fundamental programming concepts, including consideration of abstract machine models with emphasis on the memory hierarchy, basic programming constructs, functions, parameter passing, pointers and arrays, file I/O, bit-level operations, programming in the Linux environment, and lab.  

Prerequisite: (MATH 1220 or higher) or ACT Math =>25 or SAT Math Section =>590 or ACCUPLACER College-Level Math =>69.  

{Fall, Spring}

Basic elements and sources. Energy and power. Ohm's law and Kirchhoff's laws. Resistive networks, node and loop analysis. Network theorems. First-order and second-order circuits. Sinusoidal sources and complex representations: impedance, phasors, complex power. Three-phase circuits.

Prerequisite: ENG 120 or MATH 1522.

Pre- or corequisite: PHYS 1320.

Introduction to laboratory practices and the use of test equipment. Measurements on basic electrical components, dc and ac circuits using ohmmeters, voltmeters, ammeters and oscilloscopes. Circuit simulation.

Prerequisite: ENGL 1120 or ACT English =>29 or SAT Evidence-Based Reading and Writing =>700.

Pre- or corequisite: 203.

Analysis of balanced three-phase circuits. Laplace transform with applications to circuit analysis. Passive and active filters. Fourier series and Fourier transform analysis. The two-port circuits. 

Prerequisite: 203.

Pre- or corequisite: 300 or (MATH **314 and MATH **316).

{Fall, Spring}  

Introduction to elementary data structures, program design and computer-based solution of engineering problems. Topics include use of pointers, stacks, queues, linked lists, trees, graphs, software design methodology, programming in the Linux environment, and lab.  

Prerequisite: 131L or CS 152L.

Binary number systems. Boolean algebra. Combinational, sequential and register transfer logic. VHDL. Arithmetic/logic unit. Memories, computer organization. Input-output. Microprocessors.

Prerequisite: 131L or CS 152L or CS 259L.

First and second order Ordinary Differential Equations are solved with various methods including Laplace Transforms, matrices, eigenvalues and other techniques involving linear algebra. Applications will be emphasized using MATLAB.

Prerequisite: MATH 1522.

Restriction: admitted to B.S.Cp.E. Computer Engineering or B.S.E.E. Electrical Engineering.

Continuous and discrete time signals and systems; time and frequency domain analysis of LTI systems, Fourier series and transforms, discrete time Fourier series/transform, Z-transform, sampling theorem, block diagrams, modulation/demodulation and filters, Computer implementations.  

Prerequisite: 213 and 300.

Introduction to diodes, bipolar and field-effect transistors. Analysis and design of digital circuits, gates, flip-flops and memory circuits. Circuits employing operational amplifiers. Analog to digital and digital to analog converters.

Prerequisite: 206L and 213.

Analysis, design, and characterization of linear circuits including operational amplifiers. Design of biasing and reference circuits, multistage amplifiers, and feedback circuits.

Prerequisite: **321L.

Design of software systems using modern modeling techniques. Relationship between software design and process, with emphasis on UML and its interface application code. Exposure to design patterns, software frameworks, and software architectural paradigms.

Prerequisite: 231L.

An introduction to data structures and algorithms. Topics include asymptotic notation recurrence relations, sorting, hash tables, basic priority queues, balanced search trees and basic graph representation and search.

Prerequisite: 231L and MATH **327.

Pre- or corequisite: **340.

Course considers design principles, implementation issues, and performance evaluation of various software paradigms in an integrated computing environment. Topics include performance measurement and evaluation, program optimization for the underlying architecture, integration and security for large-scale software systems.

Prerequisite: 330.

Advanced combinational circuits; XOR and transmission gates; computer-based optimization methods; RTL and HDL; introduction to computer aided design; advanced sequential machines; asynchronous sequential machines; timing issues; memory and memory interfacing; programmable logic devices; and VLSI concepts.

Prerequisite: 238L.

Introduction to probability, random variables, random processes, probability distribution/density functions, expectation, correlation, power spectrum, WSS processes, confidence internals, transmission through LTI, applications of probability.  

Prerequisite: 300.

Pre- or corequisite: **314L.

Amplitude/frequency modulation, pulse position/amplitude modulation, probabilistic noise model, AWGN, Rice representation, figure of merit, phase locked loops, digital modulation, introduction to multiple access systems.

Prerequisite: **314L and **340.

Computers and Microprocessors: architecture, assembly language programming, input/output and applications. Three lectures, 3 hours lab.

Prerequisite: 206L and 238L and **321L.

Introduction to the feedback control problem. Modeling of dynamic systems in frequency and time domains. Transient and steady-state response analyses. Stability concepts. Root-locus techniques. Design via gain adjustment. Frequency response techniques. Nyquist criterion, stability margins.  

Prerequisite: **314L.

Maxwell’s equations, plane wave propagation, waveguides and transmission lines, transient pulse propagation and elementary dipole antenna.

Prerequisite: 213 and MATH 2531 and PHYS 1320.

Introduction to quantum mechanics, crystal structures, insulators, metals, and semiconductor material properties, PN junction, field effect devices.  

Prerequisite: 300 and PHYS 2310.

Provides in-depth look at various elements of power systems including power generation, transformer action, transmission line modeling, symmetrical components, pf correction, real/quadrature power calculations, load flow analysis and economic considerations in operating systems.

Prerequisite: 213.

(Also offered as CS 412)

This course is an introduction to the technical aspects of raster algorithms in computer graphics. Students will learn the foundational concepts of 2-D and 3-D graphics as they relate to real-time and offline techniques. Students will develop a video game as a final project to demonstrate the algorithms learned in class.

Prerequisite: **331 or CS 361L.

Design methodology and development of professional project oriented skills including communication, team management, economics and engineering ethics. Working in teams, a proposal for a large design is prepared in response to an industrial or in-house sponsor.

Restriction: admitted to B.S.Cp.E. Computer Engineering or B.S.E.E. Electrical Engineering, and senior standing.

Continuation of 419. Students work in teams to implement 419 proposal. Prototypes are built and tested to sponsor specifications, and reports made to sponsor in addition to a Final Report and Poster Session presentation.

Prerequisite: 419

Design of advanced analog electronic circuits. BJT and MOSFET operational amplifiers, current mirrors and output stages. Frequency response and compensation. Noise. A/D and D/A converters.

Prerequisite: **322L.

Advanced topics include: lC technologies, CAD tools, gate arrays, standard cells and full custom designs. Design of memories, PLA, I/0 and random logic circuit. Design for testability.  

Prerequisite: **321L and **338.

Management and technical issues including business conduct and ethics related to the design of large engineering projects. Student teams will address the design, specification, implementation, testing and documentation of a large hardware/software project.

Prerequisite: **335.

(Also offered as CS **481)

Fundamental principles of modern operating systems design, with emphasis on concurrency and resource management. Topics include processes, interprocess communication, semaphores, monitors, message passing, input/output device, deadlocks memory management, files system design.

Prerequisite: **331 or CS 341L.

Computer architecture; design and implementation at HDL level; ALU, exception handling and interrupts; addressing; memory; speed issues; pipelining; microprogramming; introduction to distributed and parallel processing; buses; bus protocols and bus masters. CAD project to include written and oral presentations.

Prerequisite: **338 and **344L.

Bilateral Z transforms, region of convergence, review of sampling theorem, aliasing, the discrete Fourier transform and properties, analysis/design of FIR/IIR filters, FFT algorithms spectral analysis using FFT.

(Also offered as CS **485)

Theoretical and practical study of computer networks, including network structures and architectures. Principles of digital communications systems. Network topologies, protocols and services. TCP/IP protocol suite. Point-to-point networks; broadcast networks; local area networks; routing, error and flow control techniques.

The course is an introduction to cellular telephone systems and wireless networks, drawing upon a diversity of electrical engineering areas. Topics include cellular concepts, radio propagation, modulation methods and multiple access techniques.

Prerequisite: 341.

(Also offered as PHYS 445/545) An introduction to the mathematical formalism of quantum information science, with an exploration of the key results from its application to quantum computing, quantum communication, and quantum metrology.

Introduction to design of feedback control systems. Design of compensators in the frequency and time domains. PID control and tuning. Digital implementation of analog controllers. Sensitivity and robust performance. Laboratory exercises using Matlab/Simulink and LabVIEW.  

Prerequisite: 345.

This lecture/laboratory course provides essential fundamentals for rf, wireless and microwave engineering. Topics include: wave propagation in cables, waveguides and free space; impedance matching, standing wave ratios, Z- and S- parameters.

Prerequisite: 360.

(Also offered as PHYS *463)

Electromagnetic theory of geometrical optics, Gaussian ray tracing and matrix methods, finite ray tracing, aberrations, interference and diffraction.

(Also offered as PHYS *464)

Resonator optics. Rate equations; spontaneous and stimulated emission; gas, semiconductor and solid state lasers, pulsed and mode-locked laser techniques.

Aspects of antenna theory and design; radiation from dipoles, loops, apertures, microstrip antennas and antenna arrays.

An intermediate study of semiconductor materials, energy band structure, p-n junctions, ideal and non-ideal effects in field effect and bipolar transistors.

Prerequisite: **371.

(Also offered as NSMS 574L)

Materials science of semiconductors, microelectronics technologies, device/circuit fabrication, parasitics and packaging. Lab project features small group design/fabrication/testing of MOS circuits.

Pre- or corequisite: **371.

Basic electro-optics and opto-electronics, with engineering applications. Interaction of light with matter. Introduction to optics of dielectrics, metals and crystals. Introductory descriptions of electro-optic, acousto-optic and magneto-optic effects and related devices. Light sources, displays and detectors. Elementary theory and applications of lasers, optical waveguides and fibers.

Electromagnetic theory and mechanical considerations are employed to develop models for and understanding of Transformers, Induction Machines and Synchronous Machines. Additionally, DC Machines are discussed.

Prerequisite: 381.

Pre- or corequisite: 360.

Introduces modern power conversion techniques at a lower level, dealing with basic structures of power converters and techniques of analyzing converter circuits. Students learn to analyze and design suitable circuits and subsystems for practical applications.

Prerequisite: **322L and 381.

Technical concepts of photovoltaics. Solar cell device level operation, packaging, manufacturing, designing phovoltaic system for stand-alone or grid-tied operation, some business-case analysis and some real-life scenarios of applicability of these solutions.

A detailed study of current and emerging power and energy systems and technologies. Including renewable energies, storage, Smart Grid concepts, security for power infrastructure. Software modeling of power systems and grids.

Analysis and design of practical power electronic circuits and grid or off-grid inverters. Operation and specification of power devices such as diodes, MOSFETS, IGBTs, SCRs, inductors, and transformers. Simulation of converters using SPICE.

Prerequisite: 381 and (482 or 582).

Professional practice under the guidance of a practicing engineer. Assignments include design or analysis of systems or hardware, or computer programming. A preliminary proposal and periodic reports are required. The engineer evaluates student’s work; a faculty monitor assigns grade (12 hours/week) (24 hours/week in summer session).

Offered on a CR/NC basis only.

Restriction: admitted to B.S.Cp.E. Computer Engineering or B.S.E.E. Electrical Engineering, and junior standing.

Registration for more than 3 hours requires permission of department chairperson.

A special seminar open only to honors students. Registration requires permission of department chairperson.

Open only to honors students.

Registration requires permission of the department chairperson and of the supervising professor.

State space representation of dynamical systems. Analysis and design of linear models in control systems and signal processing. Continuous, discrete and sampled representations. This course is fundamental for students in the system areas.

Introduction to the topic of optimization by the computer. Linear and nonlinear programming. The simplex method, Karmakar method, gradient, conjugate gradient and quasi-Newton methods, Fibonacci/Golden search, Quadratic and Cubic fitting methods, Penalty and Barrier methods.

This course will introduce the student to medical imaging modalities (e.g. MRI, Nuclear Imaging, Ultrasound) with an emphasis on a signals and systems approach. Topics will include hardware, signal formation, image reconstruction and application.

(Also offered as CS 512)

Covers image synthesis techniques from perspective of high-end scanline rendering, including physically-based rendering algorithms. Topics: radiometry, stochastic ray tracing, variance reduction, photon mapping, reflection models, participating media, advanced algorithms for light transport.

Linearization of nonlinear systems. Phase-plane analysis. Lyapunov stability analysis. Hyperstability and Popov stability criterion. Adaptive control systems. Adaptive estimation. Stability of adaptive control systems, backstepping and nonlinear designs.

Prerequisite: 500.

Theory and practice of feature extraction, including edge, texture and shape measures. Picture segmentation; relaxation. Data structures for picture description. Matching and searching as models of association and knowledge learning. Formal models of picture languages.

Decision functions and dichotomization; prototype classification and clustering; statistical classification and Bayes theory; trainable deterministic and statistical classifiers. Feature transformations and selection.

This course provides an introduction to the design of electronic systems that incorporate both hardware and software components.

Prerequisite: *443.

Design of advanced analog electronics circuits. BJT and MOSFET operational amplifiers, current mirrors and output stages. Frequency response and compensation. Noise. A/D and D/A converters.

This course provides an introduction to fundamental concepts in modern networking and networking pricing including the prospect theory, team theory, game theory, contract theory, network externalities and applications in the network economics field.

Prerequisite: 540.

This course provides an introduction to hardware security and trust primitives and their application to secure and trustworthy hardware systems.

This course will cover introductory material around technical cybersecurity in the internet of things. We will cover host-based attacks, network attacks, fuzzing, web attacks, and defenses thereof.

Students in this course should have an undergraduate-level (or equivalent) education in Computer Engineering or Computer Science.

This course provides an introduction to the techniques and technologies used in cloud computing. It consists of independent and intensive hands-on labs. The course emphasizes on architecture and the development of Web services.

Prerequisite: *440 or 540.

This course is an introduction to the Internet of Things (IoT), focusing on integration with cloud technologies, common IoT communication protocols, and embedded Linux.

Fundamentals of 2D signals and systems. Introduction to multidimensional signal processing. Applications in digital image processing. Image formation, representation and display. Linear and nonlinear operators in multiple dimensions. Orthogonal transforms representation and display. Image analysis, enhancement, restoration and coding. Students will carry out image processing projects.

(Also offered as PHYS 534)

Plasma parameters, adiabatic invariants, orbit theory, plasma oscillations, hydromagnetic waves, plasma transport, stability, kinetic theory, nonlinear effects, applications.

Satellite communication systems provide vital and economical fixed and mobile communication services over large coverage areas. In this course, students learn the fundamentals and techniques for the design and analysis of satellite communication systems.

Prerequisite: 341 and (560/460 or 569/469).

Computational aspects of engineering problems. Topics include machine models and computability, classification and performance analysis of algorithms, advanced data structures, approximation algorithms, introduction to complexity theory and complexity classes.

Course provides an in-depth analysis of computer architecture techniques. Topics include high speed computing techniques, memory systems, pipelining, vector machines, parallel processing, multiprocessor systems, high-level language machines and data flow computers.

Hilbert spaces, orthogonal basis, generalized sampling theorem, multirate systems, filterbanks, quantization, structures for LTI systems, finite word-length effects, linear prediction, min/max phase systems, multiresolution signal analysis.

Research, design and implementation of high-performance computer networks and distributed systems. High speed networking technologies, multimedia networks, enterprise network security and management, client/server database applications, mobile communications and state-of-the-art internetworking solutions.

Axiomatic probability theory, projection theorem for Hilbert spaces, conditioned expectations, modes of stochastic convergence, Markov chains, mean-square calculus, Wiener filtering, optimal signal estimation, prediction stationarity, ergodicity, transmission through linear and nonlinear systems, sampling.

Elements of information theory and source coding, digital modulation techniques, signal space representation, optimal receivers for coherent/non-coherent detection in AWGN channels, error probability bounds, channel capacity, elements of block and convolutional coding, fading, equalization signal design.

Prerequisite: 541.

(Also offered as PHYS 545/445)

An introduction to the mathematical formalism of quantum information science, with an exploration of the key results from its application to quantum computing, quantum communication, and quantum metrology.

Hermite, Smith and Smith-McMillan canonic forms for polynomial and rational matrices. Coprime matrix-fraction representations for rational matrices. Bezout identity. Poles and zeros for multivariable systems. Matrix-fraction approach to feedback system design. Optimal linear-quadratic-Gaussian (LQG) control. Multivariable Nyquist stability criteria.

An introduction to information theory. Fundamental concepts such as entropy, mutual information, and the asymptotic equipartition property are introduced. Additional topics include data compression, communication over noisy channels, algorithmic information theory, and applications.

Prerequisite: 340 or equivalent.

551. Problems . (1-6 to a maximum of 9 Δ)

(Also offered as PHYS 554)

Diffractions theory, coherence theory, coherent objects, and incoherent imaging, and polarization.

Mathematical foundations for engineering electromagnetics: linear analysis and method of moments, complex analysis and Kramers-Kronig relations, Green’s functions, spectral representation method and electromagnetic sources.

Principles of pulsed power circuits, components, systems and their relationship to charged particle acceleration and transport. Energy storage, voltage multiplication, pulse shaping, insulation and breakdown and switching. Single particle dynamics and accelerator configurations.

Overview of physics of particle beams and applications at high-current and high-energy. Topics include review of collective physics, beam emittance, space-charge forces, transport at high power levels, and application to high power microwave generation.

Prerequisite: 557.

(Also offered as PHYS 559)

Students do research and/or development work at a participating industry or government laboratory in any area of optical science and engineering.

Maxwell’s equations, electromagnetic interaction with materials, the wave equation, plane wave propagation, wave reflection and transmission, vector potentials and radiation equations, electromagnetic field theorems, wave propagation in anisotropic media and metamaterials, period structures, dielectric slab waveguides.

Prerequisite: 555.

Course will cover rf design techniques using transmission lines, strip lines and solid state devices. It will include the design of filters and matching elements required for realizable high frequency design. Amplifiers, oscillators and phase lock loops are covered from a rf perspective.

Computational techniques for partial differential and integral equations: finite-difference, finite-element, method of moments. Applications include transmission lines, resonators, waveguides, integrated circuits, solid-state device modeling, electromagnetic scattering and antennas.

Prerequisite: 561.

Optical propagation in free space, colored dielectrics, metals, semiconductors, crystals, graded index media. Radiation and guided modes in complex structures. Input and output coupling, cross-coupling mode conversion. Directional couplers, modulators, sources and detectors.

Optical waveguides, optical fiber attenuation and dispersion, power launching and coupling of light, mechanical and fiber lifetime issues, photoreceivers, digital on-off keying, modulation methods, SNR and BER, QAM and M-QAM, modulation methods, SNR, and BER, intersymbol interference (impact on SNR), clock and data recovery issues, point-to-point digital links, optical amplifiers theory and design (SOA, EDFA, and SRA), simple WDM system concepts, WDM components.

Detector architectures for mid-infrared wavelengths. Review of different technologies and figures of merit. Design problem to demonstrate an infrared imaging subsystem using commercial off-the-shelf components.

Prerequisite: *463 or PHYS *463.

569 / 469. Antennas for Wireless Communications Systems . (3) Aspects of antenna theory and design; radiation from dipoles, loops, apertures, microstrip antennas and antenna arrays.

Theory and operation of optoelectronic semiconductor devices; semiconductor alloys, epitaxial growth, relevant semiconductor physics (recombination processes, heterojunctions, noise, impact ionization), analysis of the theory and practice of important OE semiconductor devices (LEDs, Lasers, Photodetectors, Solar Cells).

Prerequisite: 471 or 572.

Crystal properties, symmetry and imperfections. Energy bands, electron dynamics, effective mass tensor, concept and properties of holes. Equilibrium distributions, density of states, Fermi energy and transport properties including Boltzmann’s equation. Continuity equation, diffusion and drift of carriers.

Prerequisite: *471.

Review of the evolution of VLSI technology and basic device physics. Detailed analysis of MOSFET devices, CMOS device design including device scaling concepts.

Carrier generation and recombination, photon generation and loss in laser cavities, density of optical modes and blackbody radiation, radiative and non-radiative processes, optical gain, spontaneous and stimulated emission, Fermi’s golden rule, gain and current relations, characterizing real diode lasers, dynamic effects, rate equation; small signal and large signal analysis, radiative intensity noise and linewidth.

Prerequisite: 572.

(Also offered as BIOM, BME, NSMS 581)

Intended for students planning careers combining engineering, materials science, and biomedical sciences. Covers synthesis, nanocrystals characterization, biofunctionalization, biomedical nanosensors, FRET-based nanosensing, molecular-level sensing/imaging, and applications in cell biology, cancer diagnostics and therapy, neuroscience, and drug delivery.

Pre- or corequisite: 582 and 583 and 584.

Prerequisite: 381 and (582 or 482).

Advanced topics in complex systems including but not limited to biological systems social and technological networks, and complex dynamics.

595 / 495. Special Topics . (1-4 to a maximum of 15, 1-4 to a maximum of 9 Δ)

599. Master's Thesis . (1-6, no limit Δ) Offered on a CR/NC basis only.

(Also offered as ANTH 620, BIOL 520, CS 520, STAT 520)

Varying interdisciplinary topics taught by collaborative scientists from UNM, SFI, and LANL.

Advanced topics including advanced computer architecture, networks, distributed computing, large-scale resource management, high-performance computing and grid-based computing.

Prerequisite: 537.

Prerequisite: 538.

Hypothesis testing; Karhunen-Loeve representation; optimal detection of discrete- and continuous-time signals; ML, MMSE, and MAP estimation; sufficient statistics, estimation error bounds; Wiener and Kalman-Bucy filtering; detection/receivers for multiuser and multipath fading channels.

Prerequisite: 546.

651. Problems . (1-6 to a maximum of 9 Δ)

Topics include advanced antenna theory, electromagnetic scattering and propagation, electromagnetic compatibility, low temperature plasma science, advanced plasma physics, and other subjects in applied electromagnetics.

699. Dissertation . (3-12, no limit Δ) Offered on a CR/NC basis only.

Course Search:

Keyword search:.

MSC11 6325 1 University of New Mexico Albuquerque , NM 87131

Work Phone: (505) 277-8900 Fax Fax: (505) 277-6809

© The University of New Mexico, Albuquerque, NM 87131, (505) 277-0111 New Mexico's Flagship University

• Accessibility
• Contact UNM