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VLSI Architectures for Wireless Communications and Digital Signal Processing

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section " Circuit and Signal Processing ".

Deadline for manuscript submissions: closed (31 August 2022) | Viewed by 16807

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Dear Colleagues,

Due to the relentless growth of computational complexity, state-of-the-art technologies cannot be realized unless they are accelerated by very-large-scale-integration (VLSI) circuits. For instance, 5G telecommunications necessitate application-specific integrated circuits (ASICs) to achieve data rates over tens of gigabits per second. The Internet-of-Things (IoT) systems connecting a massive number of edge devices also demand highly efficient hardware to accommodate data transfer within a few milliseconds under a limited power budget. Computer-vision applications based on deep neural networks are so computationally intensive that they incur orders-of-magnitude more operations than ever before. To facilitate the realization of such cutting-edge technologies, considerable attention should be paid to the development of efficient VLSI architectures.

This Special Issue solicits original and unpublished papers on high-performance and low-power VLSI architectures and the relevant algorithmic optimizations in the field of wireless communications and digital signal processing.

The topics of interest include but are not limited to:

• VLSI architectures for 5G and 6G telecommunications;
• FPGA and ASIC implementations of signal-processing systems;
• Baseband signal processing for communication systems;
• Circuits and systems for the Internet-of-Things (IoT);
• VLSI architectures for machine learning and artificial intelligence;
• Application-specific instruction-set processors for digital signal processing;
• Hardware-friendly algorithms and optimization techniques;
• Embedded systems on chip (SoCs) for signal-processing applications.

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Low-cost low-power approximated VLSI architecture for high-quality image scaling in mobile devices

• Original Research Paper
• Published: 06 February 2023
• Volume 20 , article number  11 , ( 2023 )

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• Venkata Siva Midde   ORCID: orcid.org/0000-0003-0226-5873 1 &
• E. P. Jayakumar   ORCID: orcid.org/0000-0002-6692-8720 1  

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This paper proposes three pipeline VLSI architectures for high-quality image scaling. The proposed architectures use low-complexity v-model spatial sharpening filter, modified edge detection, and simplified bilinear interpolation. Low complexity v-model spatial sharpening filter is obtained by modifying the 3  \(\times\)  3 sharpening kernel to x-model and then to v-model. This sharpening filter enhances the center pixel intensity value relative to the nearest pixels. The modified edge detection technique needs less hardware to find the sharp change in the pixel values. The number of multipliers required for bilinear interpolation is reduced by performing algebraic manipulations. Matlab tool is used analyze the scaled image quality with Peak Signal to Noise Ratio (PSNR) and Structural Similarity (SSIM) parameters. The proposed three VLSI architectures are described using Verilog HDL (hardware description language) and synthesized using Cadence genus compiler using GPDK 90 nm technology. One of the proposed architectures requires 8981 (µm 2 ) area and consumes 1.90 (mW) power, which is less when compared to those of the existing architectures.

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High Level Synthesis of VLSI Based Image Scaling Architecture for High Definition Displays

FPGA realization of an efficient image scalar with modified area generation technique

VLSI Architecture for Image Scaling in Multimedia Applications

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Acknowledgements

The authors would like to thank SMDP-C2SD Project, NIT Calicut, funded by MeitY, Govt. of India, for providing research facility and technical support.

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Midde, V.S., Jayakumar, E.P. Low-cost low-power approximated VLSI architecture for high-quality image scaling in mobile devices. J Real-Time Image Proc 20 , 11 (2023). https://doi.org/10.1007/s11554-023-01282-y

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Reversible logic gates and applications – a low power solution to vlsi chips.

© 2024 The authors. This article is published by IIETA and is licensed under the CC BY 4.0 license ( http://creativecommons.org/licenses/by/4.0/ ).

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In recent years, reversible logic gates have garnered significant interest because of their potential to decrease energy consumption and meet the growing need for low-power computing systems. Unlike conventional logic gates, reversible logic gates ensure that no information loss happens during computation, allowing for the reversal of the entire computation process. This unique characteristic opens up new avenues for developing energy-efficient digital circuits. This review paper serves as a vital contribution to the field by addressing a noticeable gap in the existing literature regarding reversible logic gates. The study not only comprehensively analyzes the array of reversible logic gates available but also underscores their practical applications and significance. It encompasses a wide variety of reversible logic gates, including Toffoli gates, Fredkin gates, and newer innovations. It is found that Toffoli gates outperformed in terms of gate count and quantum cost reduction, making them a preferred choice for quantum circuit optimization. Additionally, Fredkin gates showed exceptional performance in specific applications, like data swapping and quantum state control. The digital circuits like adders, multiplexers, ALU etc. are successfully designed using reversible gates like HNG, DKG etc. The significant gap this study fills lies in the need for a consolidated and in-depth analysis of the state-of-the-art reversible logic gates and their real-world utility. While prior research has discussed these gates individually, this paper takes a novel approach by offering a holistic assessment of their performance, quantum cost, gate count, and practical applications, thereby presenting a comprehensive resource for researchers, engineers, and designers in the field. This innovative contribution plays a pivotal role in shaping the progress of energy-efficient and quantum computing systems as well as in optimizing VLSI chip designs for various applications, with a particular emphasis on enhancing cryptographic and data processing capabilities. The findings of this review aim to stimulate further research and development in reversible computing, contributing to the advancement of energy-efficient and information-preserving computing systems.

reversible logic gates, Toffoli gate, Fredkin gate, power dissipation, quantum computing, quantum cost, reversible logic application, low power design, cryptography

Gordon Moore, one of the co-founders of Intel Corporation, made a famous prediction in 1965 that came to be known as Moore's Law [1]. He noted that the doubling of transistors on a silicon chip occurred at approximately two-year intervals, resulting in a notable augmentation of computing capabilities. The reduction in feature size has led to several implementation and operational difficulties. It is difficult for CMOS technology to continue to the required level of growth. Since the power consumption of CMOS circuit increases with clock frequency and the frequency determines the computation speed and performance, an increase in performance also increases the power consumption [2]. The challenge is the unsustainable relationship between power consumption versus performance.

The Landauer principles [3, 4] states that the removal of one bit of information during an irreversible computation necessitates a minimum energy dissipation of approximately kT ln(2), where 'k' represents the Boltzmann constant, and 'T' denotes the temperature in Kelvin. This principle implies that for each bit erased, a minimum of kT ln(2) joules of energy must be dissipated in the form of heat. In 1973, Charles H. Bennett published a groundbreaking study titled "Logical Reversibility of Computation," which laid the foundation for the field of reversible computing [5]. Bennett's study [6] explored the theoretical underpinnings and implications of reversible computation, focusing on its fundamental connection to thermodynamics and information theory. In the study, Bennett demonstrated that logical reversibility is a key concept in achieving energy-efficient computation. The concept of reversible computation, which he introduced, involves a scenario in which every computational step is entirely invertible. This feature permits the retrieval of the initial state from the final state with no information loss. Bennett's work showed that reversible computation has significant implications for reducing energy dissipation in computing systems.

Reversible logic, also known as reversible computing or reversible gates, is a computing paradigm that focuses on designing logic circuits or systems that can perform computations without losing information [7]. Unlike conventional logic gates, which are irreversible that discard or overwrite bits, and can result in information loss through dissipative processes like heat generation, reversible logic gates guarantee the individual recovery of all input information from the output, establishing a direct one-to-one relationship between the input and output. This property enables the computation to be reversible, allowing the system to be able to "undo" operations and revert back to the original state. This preservation of information allows for energy conservation since no energy is dissipated as heat due to information loss. The major advantages which one can gain by using reversible logic circuits are:

Energy efficiency: Reversible logic gates are engineered with the goal of reducing energy dissipation [8] while preserving all information throughout computation. As the feature size decreases, power density and leakage currents become more significant challenges. By adopting reversible logic, which inherently aims to conserve energy, it is possible to reduce power consumption and mitigate some of the energy-related challenges associated with scaling [9].

Reduced gate count: Reversible logic gates typically have fewer gates compared to their irreversible counterparts for achieving the same functionality. This reduction in gate count can be advantageous in VLSI chip design, as it helps to minimize the increasing complexity and fabrication challenges caused by shrinking feature sizes. Fewer gates lead to simpler designs, which can enhance manufacturability, yield, and overall circuit performance.

Signal integrity: Reversible logic gates often exhibit lower fan-out and reduced signal propagation delays compared to irreversible gates [10]. These characteristics can help maintain better signal integrity and alleviate some of the challenges related to interconnect delays, crosstalk, and power supply noise. By reducing the impact of signal integrity issues, reversible logic can contribute to more reliable and efficient circuit operation.

Quantum computing considerations: Reversible logic gates have a vital role within the domain of quantum computing [11], which utilizes quantum bits (Qubits) [12-14] that must maintain coherence throughout computation. While reversible logic in classical VLSI chips does not directly address quantum computing challenges, the experience gained from reversible logic design techniques and circuit optimization approaches can be valuable for developing future quantum computing technologies.

Reversible logic along with process technology advancements, device engineering, circuit design methodologies, and manufacturing techniques offers potential benefits in terms of energy efficiency, gate count reduction, and signal integrity. Reversible logic has the potential to drastically reduce power consumption in computing systems, making it a promising approach for energy-efficient computing, especially in scenarios where power consumption is a critical factor, such as in quantum computing, nanotechnology, and low-power embedded systems [15]. Reversible logic gates, such as the Feynman gate, Fredkin gate, Toffoli gate, and Peres gate, Feynman double gate [16-18], have been developed as building blocks for reversible circuits. These gates have the property of being reversible, allowing computations to be performed with guaranteed information preservation. Research in the area of reversible logic encompasses various aspects, including circuit design, synthesis, optimization, fault tolerance, and applications. Researchers continue to explore and develop reversible logic design techniques, algorithms, and architectures to harness its benefits in various applications. Currently, reversible logic is used to implement various combinational and sequential circuits like ALU, counters, encoders, flip flops, fault checkers, etc. [19]. Some research directions and recent advancements in the field are as follows:

Circuit design and synthesis: Researchers are developing efficient methodologies for designing and synthesizing reversible circuits [20-28]. This involves the exploration of novel gate libraries, reversible gates, and building blocks that can perform computations without any loss of information.

Optimization techniques: Several optimization techniques are being explored to lessen the number of gates, garbage outputs, and quantum cost of reversible circuits [29-40]. This includes approaches like gate-level optimization, logic synthesis, gate swapping, and technology mapping.

Quantum reversible logic: Reversible logic plays a significant role in quantum computing [39]. Researchers are investigating reversible logic synthesis techniques tailored for quantum circuits. The objective is to minimize the quantum cost and improve the overall efficiency of quantum computations [41, 42].

Fault-tolerant reversible logic: Fault tolerance is crucial in any computing system. Researchers are studying fault-tolerant designs and fault diagnosis techniques for reversible logic circuits. Redundancy-based approaches, error detection and correction codes, and fault modeling are areas of active research in the area of reversible logic [43-46].

Reversible logic applications: Reversible logic has applications in various fields, including cryptography, image processing, data compression, quantum computing, and low-power computing [47-50]. Research focuses on developing efficient reversible algorithms and architectures for these applications.

Quantum computing and reversible logic: Reversible logic is deeply connected to quantum computing due to the reversible nature of quantum operations [51-56]. Research explores the relationship between reversible logic and quantum computing, including the development of reversible quantum gates and reversible circuit synthesis for quantum algorithms.

Reversible logic and energy efficiency: One of the key motivations behind reversible logic is energy efficiency [57]. Researchers investigate the impact of reversible logic in reducing power consumption, heat dissipation, and overall energy requirements in different computing paradigms, such as classical and quantum computing.

These are just a few research directions within the area of reversible logic. This field draws attention from all disciplines involving aspects of computer science, electrical engineering, quantum physics, and information theory. Ongoing research aims to improve the theoretical foundations, design methodologies, and practical implementation of reversible logic, with the goal of realizing energy-efficient computing systems. In this study, our primary objective is to comprehensively analyze the performance and applications of various reversible logic gates. Specifically, we aim to address the following aspects:

•The quantum cost and gate count associated with different reversible logic gates.

•Real-world applications and implications of these gates, with a particular focus on their relevance in quantum computing, energy-efficient computing, and VLSI chip design.

This paper is structured as follows: Section 2 provides an in-depth analysis of the basic parameters associated with various reversible logic gates. In Section 3, we explore all gates invented till date. Section 4 offers a comparative analysis of our findings and highlights the practical benefits and implications of our research along with its popular applications. Finally, in Section 5, we conclude by summarizing our work and underscoring its novelty and significance.

As defined in literature [58], there are several terminologies and parameters related to reversible logics. In this section, the terminologies are explained in detail:

Figure 1 . Reversible logic gate

The reversible logic gate is a logic device having n inputs and n outputs as shown in Figure 1. The 'n' inputs are a combination of 'a' primary inputs and 'b' constant inputs (a+b=n), and similarly ‘n’ outputs on the output side, which are made up of 'x' primary outputs and 'y' garbage outputs such that x+y=n. The reversible circuit should be designed in such a way that it requires reversible logic gates, input constant, and garbage outputs minimum.

Constant inputs: These are fixed inputs provided to the reversible gate that do not change. They can be used to control the gate's behavior or enforce specific logic operations. They are essential for achieving specific computations, optimizing circuit performance, and enhancing the flexibility and programmability of reversible logic circuits.

Garbage outputs: In reversible computing, garbage outputs refer to the bits that do not contribute to the final output and are essentially discarded. Minimizing the number of garbage outputs is crucial in designing efficient reversible circuits. One has to preserve the following relation while designing a reversible circuit:

inputs+constant inputs=outputs+garbage outputs.

Fan-out: In reversible logic, the fan-out parameter refers to the maximum number of gates that can directly receive the output of a particular gate without any additional measures, such as auxiliary gates or circuit modifications; while maintaining reversibility and the direct correspondence between input and output states remains a one-to-one relationship. Unlike classical logic gates, achieving direct fan-out in reversible logic is challenging due to the requirement of preserving information and reversibility. The reversible gates used in the circuit design should ensure that each input state maps to a unique output state, making it difficult to directly connect multiple gates to a single output without violating this property. Fan-out, the number of times an output is used as an input in reversible logic circuits, impacts performance and design. High fan-out can increase gate complexity because gates with multiple inputs (controlled by the fan-out) may require additional resources to maintain reversibility; increase propagation delay as when an output is connected to multiple inputs of other gates (high fan-out), it can slow down the circuit's overall operation because the signal must fan out to multiple destinations, potentially causing delays; increase quantum cost as more gates may be needed to achieve the same functionality and the need to manage garbage outputs. Designers must balance fan-out to optimize circuit efficiency while preserving reversibility.

Flexibility: Flexibility shows the universality of reversible logic gates. Flexibility in reversible logic gates refers to their ability to perform a wide range of computational tasks while still adhering to the principles of reversibility. This includes not just performing basic logical operations but also more complex transformations and computations. A flexible reversible logic gate should be capable of emulating any other reversible or irreversible gate or circuit. The Toffoli gate, for example, is a commonly used universal reversible gate that can emulate various other gates and functions. To achieve reversibility, we need minimal garbage output, minimal delay, and no feedback/loops.

Delay: The delay parameter refers to the time required for a reversible gate or circuit to propagate its input changes to the output. It represents the time delay experienced by the signals passing through the gate or circuit. The definition relies on two underlying premises: (i) Each gate carries out the computation within a single unit of time, and (ii) All inputs to the circuit are accessible prior to the commencement of computation.

Gate count: It is measure of the total number of reversible gates used in a circuit. It indicates the complexity of the circuit and affects factors such as circuit size, power consumption, and delay.

Hardware complexity: Each reversible gate performs a specific logic operation, such as AND, OR, EX-OR, or NOT. The gate's functionality is defined by the way it transforms the input signals into output signals. For example, the Toffoli gate performs a controlled NOT operation, while the Fredkin gate swaps the values of two input bits based on a control bit. The hardware complexity determines the number of logical operations performed in the circuit, such as AND, OR, EX-OR. In the realm of reversible logic gates, hardware complexity can significantly impact:

•Performance: Complex gates can slow down the circuit operation.

•Quantum cost: High complexity can raise the quantum cost in quantum computing.

•Gate count: More complex gates demand more resources, affecting cost and scalability.

•Reliability: Complexity can increase error probabilities affecting reliability.

•Resource efficiency: Simplifying gates is crucial for efficient resource utilization.

•Ease of programming: Simpler gates are easier to program and maintain, thereby reducing development costs.

Reversibility degree: The reversibility degree measures the extent to which a circuit or gate is reversible. It refers to the ratio of the number of input combinations that yield unique output combinations to the total number of possible input combinations.

Reversibility Degree=(Number of Unique Output Combinations)/(Total Number of Possible Input Combinations)

For example, as for a 2×2 reversible Peres gate, there will be 4 unique input and output combinations, hence its reversibility degree is 100%.

Quantum cost: Quantum cost measures the computational resources required to implement a reversible logic gate. It is often quantified in terms of the number of two qubit gates or elementary gates (such as NOT, CNOT, and Toffoli gates) needed to construct a given reversible gate. Quantum cost optimization is an important consideration in reversible logic design, as minimizing the quantum cost leads to more efficient and less resource-intensive implementations. Various techniques and algorithms, such as synthesis and optimization tools, can be employed to reduce the quantum cost of reversible logic circuits. Strategies for optimization include gate count reduction, gate synthesis, compiler optimization, heuristic methods, and the use of error correction techniques. Ongoing research and libraries of pre-optimized gates contribute to improving efficiency in quantum computation.

In summary, each parameter impacts the efficiency and effectiveness of reversible logic gates by influencing factors like speed, resource consumption, reliability, ease of design and maintenance, and suitability for various applications. Reducing gate count, fan-out, hardware complexity, garbage output, quantum cost, and resource demands all lead to more efficient and effective circuits.

In the next section, the discussion on reversible gates available in the literature till now is presented.

The methodology for this research paper involves a comprehensive and systematic analysis of various reversible logic gates and their applications mentioned in research papers. The selection of reversible logic gates for analysis was based on several key criteria, including their historical significance, prevalence in modern applications, and representation of different gate types. The chosen gates represent a spectrum of gate functionalities, including Toffoli gates, Fredkin gates, and newer innovations, allowing for a comprehensive analysis of the field. The applications of reversible logic gates were analyzed through a multi-faceted approach. This involved studying their use in quantum computing, energy-efficient computing systems, and VLSI chip design. A comparative analysis was conducted to assess their performance in these domains. Real-world implementations and case studies were also examined to understand the practical implications. The upcoming subsection introduces reversible gates categorized by the dimensions of their inputs and outputs. According to the latest developments in the field, the largest input and output size achievable stands at 6.

3.1 2×2 reversible logic gates

3.1.1 CNOT / FEYNMAN gate

The CNOT gate, short for Controlled-NOT gate [59], is a fundamental reversible logic gate (Figure 2) commonly used in reversible computing and quantum computing. This gate is a 2×2 gate having two inputs clubbed together in the vector form as In={X, Y} and similarly outputs as Out={X, X$\oplus$Y}. It operates on two input bits, a control bit (X) and a target bit (Y), and produces two output bits, maintaining the same control bit and possibly flipping the target bit.

The behavior of the CNOT gate can be summarized as follows:

If the control bit (X) is 0, the output remains the same as the input: (X, Y) → (X, Y).

If the control bit (X) is 1, the target bit (Y) is flipped: (X, Y) → (X, NOT(Y)).

In other words, the CNOT gate copies the value of the control bit to the target bit when the control bit is 1, and leaves the target bit unchanged when the control bit is 0. The CNOT gate is a fundamental component in quantum error correction codes, such as the surface code. The quantum cost is 1. It is used to propagate errors and perform syndrome measurements, allowing the detection and correction of errors that occur during quantum computations. Feynman gate is used for duplication of outputs.

Figure 2. CNOT gate

3.2 3×3 reversible logic gates

3.2.1 TOFFOLI gate

The Toffoli gate (Figure 3), also known as the Controlled-Controlled-Not (CCNOT) gate, is a fundamental gate in quantum computing. It is named after the physicist Tommaso Toffoli, who first introduced it in 1980. This gate is characterized by 3 inputs and 3 outputs as its 3×3 gate. The inputs are clubbed together to represent in the form of a vector as In={X, Y, Z} and the output as Out={X, Y, XY$\oplus$Z}. The last bit is the target bit, the rest are control bits, when the control bit is 1, the target bit is inverted. The quantum cost is 5. Toffoli gate can be used to realize any function, hence it is known as a universal reversible gate [60]. It is used for quantum error correction applications [61].

Figure 3. TOFFOLI gate

3.2.2 FREDKIN gate

The Fredkin gate as shown in Figure 4, also known as the Controlled-Swap (CSWAP) gate or the Controlled-Permutation gate, is a reversible three-Qubits gate named after the computer scientist Edward Fredkin who invented it in 1982 [17]. The set of input are In={X, Y, Z} and the outputs are Out={X, XY$\oplus$XZ, X’Z$\oplus$XY}. The input X is mapped directly to the output A. If X=0, Y is mapped to B, Z is mapped to C. If X=1, a swap operation is performed and Y is mapped to C and Z is mapped to B. Therefore, it is also known as a Controlled SWAP gate. The quantum cost is 5. Fredkin gate is used to preserve parity [62].

Figure 4. FREDKIN gate

3.2.3 PERES gate

The PERES gate (Figure 5), also known as the Peres-Horodecki gate, is a two-qubit gate named after Asher Peres and Michał Horodecki, who contributed to its study in 1996 [16]. It is an entanglement detection gate that determines whether two Qubits are entangled or separable. The input is represented as In={X, Y, Z} and the output is represented as Out={X, X$\oplus$Y, XY$\oplus$Z}. The quantum cost is 4. TRG gate is used for the implementation of a full subtractor. Peres gate can be used to realize functions like NOT, AND, NAND, XOR [61].

Figure 5. PERES gate

3.2.4 Double Feynman gate

The input is represented as In={X, Y, Z} and the output is represented as Out={X, X$\oplus$Y, X$\oplus$Z}. The quantum cost is 2. Double Feynman gate shown in Figure 6 is a parity preserving gate [63, 64].

Figure 6. DOUBLE FEYNMAN gate

3.2.5 BJN gate

In Figure 7, BJN gate is shown. The input is represented as In={X, Y, Z} and the output is expressed as Out={X, Y,(X+Y)$\oplus$Z}. The quantum cost is 5 [62].

Figure 7. BJN gate

3.2.6 RMUX 1 gate

The input is represented as In={X, Y, Z} and the output is represented as Out={X, X’Y+XZ, X’Z+XY'}. The quantum cost is 4. RMUX1 gate as shown in Figure 8 works as a 2:1 MUX, where X is the select line and Y&Z are the two inputs [65].

Figure 8. RMUX1 gate

3.2.7 TRG gate

The block diagram of TRG gate is shown in Figure 9. The input is represented as In={X, Y, Z} and the output is represented as Out={X, X$\oplus$Y, XY’$\oplus$Z'}. The quantum cost is 4. TRG gate is used for the implementation of a full subtractor circuit [65].

Figure 9. TRG gate

3.2.8 NEW gate

The block diagram of NEW gate is shown in Figure 10. The input is represented as In={X, Y, Z} and the output is represented as Out={X, XY$\oplus$Z, X’Z’$\oplus$Y’} [65].

Figure 10. NEW gate

3.2.9 SAM gate

The input vector In={X, Y, Z} and the output vector Out={X’, X’Y$\oplus$XZ’, X’Z$\oplus$XY} for the SAM Gate is shown in Figure 11 [64].

3.2.10 NFT gate

New fault tolerant gate is a gate for parity preserving. Its block diagram is shown in Figure 12. The input is represented as In={X, Y, Z} and the output is represented as Out={X$\oplus$Y, YZ’$\oplus$XZ’, YZ$\oplus$XZ’} [63].

Figure 11. SAM gate

Figure 12. NFT gate

3.2.11 RC-I gate

RC-I gate is a single bit comparator circuit. Figure 13 displays its block diagram. The input is represented as In={X, Y, Z} and the output is represented as Out={X, X’Y$\oplus$Z, XY’$\oplus$Z}. It compares X and Y [66].

Figure 13. RC I gate

3.2.12 UPG gate

Universal programmable gate (UPG) as the name implies can be used to implement logical functions like NAND, AND OR, and NOR. The input is represented as In={X, Y, Z} and the output is represented as Out={X, (X+Y)$\oplus$Z, XY$\oplus$Z}. It can perform logical operations at low quantum cost. Its block diagram is shown in Figure 14 [65].

Figure 14. UPG Gate

3.2.13. YAG gate

The input is represented as In={X, Y, Z} and the output is represented as Out={X, (X$\oplus$Y)$\oplus$(XY$\oplus$Z), XY$\oplus$Z}.

YAG is used to realize AND and OR functions. Its block diagram is shown in Figure 15 [67].

3.2.14 RMUX2 gate

The input is represented as In={X, Y, Z} and the output is represented as Out={X, XYv+XZ, X$\oplus$(Y$\oplus$Z)}. Its quantum cost is 4. In this gate, X is the select line, the gate gives the multiplexed output of Y and Z Its block diagram is shown in Figure 16 [65].

Figure 15. YAG gate

Figure 16. RMUX2 gate

3.2.15 HAS gate

Half Adder Subtraction gate has quantum cost 5. The input is represented as In={X,Y,Z} and the output is represented as Out={X, X$\oplus$Y$\oplus$Z, X$\oplus$Y$\oplus$X’$\oplus$Z}. HAS gate is used to implement BCD adder, carry skip BCD adder circuit, half adder, and full subtractor [68]. Its block diagram is shown in Figure 17.

Figure 17. HAS gate

3.3 4×4 reversible logic gates

3.3.1 Double Peres gate

Double Peres gate is used to implement the full adder [69]. Figure 18 represents its block diagram. The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, W$\oplus$X, W$\oplus$X$\oplus$Z, (W$\oplus$X)Z$\oplus$WX$\oplus$Y}. The quantum cost is 6.

Figure 18. DPG gate

3.3.2 MRG gate

Marrison-Ranganathan gate (MRG) is a programmable gate. The input is represented as In={W, X, Y, Z} and the output is represented as Out ={W, W$\oplus$X, (W$\oplus$X)$\oplus$Y, (WX$\oplus$Z)$\oplus$(W$\oplus$X)$\oplus$Y}. The quantum cost is 6. The 4 operations that MRG gate can perform are OR, NOR, XNOR, and XOR. Its block diagram is shown in Figure 19 [70].

Figure 19. MRG gate

3.3.3 SAYEM gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, W’X$\oplus$WY, W’X$\oplus$WY$\oplus$Z, WX$\oplus$W’Y$\oplus$Z}. The Sayem gate is a versatile component that can be employed in the construction of reversible standard sequential circuits, including popular flip-flop designs such as the T flip-flop and D flip-flop, in conjunction with the Feynman gate. This combination of components allows for the creation of advanced sequential logic circuits with the unique property of reversibility. Its block diagram is shown in Figure 20 [60].

Figure 20. SAYME gate

3.3.4 TSG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, W’Y$\oplus$X’, (W’Y$\oplus$X’)$\oplus$Z, (W’Y$\oplus$X’)Z$\oplus$WX$\oplus$Y} . The TSG gate, in conjunction with the CNOT (Controlled-NOT) gate, serves as the fundamental building block for the implementation of a full adder. This powerful combination of gates enables the creation of a full adder circuit, a fundamental component in digital arithmetic. Its block diagram is shown in Figure 21 [71].

Figure 21. TSG gate

3.3.5 DKG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={X, W’Y+WZ’, (W$\oplus$X)(Y$\oplus$Z)$\oplus$YZ, X$\oplus$Y$\oplus$Z}. DKG gates can singly work as either a full adder or a full subtractor. W is the control line, if W is set to 0, it will work as full adder, and if W is set to 1, it will work as full subtractor. Its block diagram is shown in Figure 22 [71, 72].

Figure 22. DKG gate

3.3.6 SCL gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, X, Y, W(X+Y)$\oplus$Z}. SCL gate is used to add 6 to the sum for correcting it to get the actual BCD sum. Its block diagram is shown in Figure 23 [69].

Figure 23. SCL gate

3.3.7 BVF gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, W$\oplus$X, Y, Y$\oplus$Z}. BVF is a double XOR gate. The BVF gate serves the purpose of extracting essential inputs to fulfill the fan-out requirements. Its block diagram is shown in Figure 24 [73].

Figure 24. BVF gate

3.3.8 ALG gate

The input is represented as In={W,X,Y,Z} and the output is represented as Out={W, W$\oplus$X$\oplus$Y, (W$\oplus$X)Y$\oplus$(WX$\oplus$Z), (W’$\oplus$X)Y$\oplus$(W’X$\oplus$Z)}. The ALG gate can perform multiple operations like full adder, full subtractor, XOR, NAND, and NOR. Its block diagram is shown in Figure 25 [71].

Figure 25. ALG gate

3.3.9 PPHCG gate

Parity Preserving Hamming Code Generator (PPHCG) gate preseves parity. The input is represented as In={W, X, Y, Z} and the output is represented as Out={X$\oplus$Y$\oplus$Z, W$\oplus$X$\oplus$Y, W$\oplus$X$\oplus$Z, W$\oplus$Y$\oplus$Z}. The quantum cost is 6. A PPHCG is used to ensure fault tolerance in Hamming error coding and detection circuits by preserving the input data's parity, enhancing the accuracy and reliability of error detection and correction. Its block diagram is shown in Figure 26 [63].

Figure 26. PPHCG gate

3.3.10 IG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={X, W$\oplus$X, WX$\oplus$Y, XZ$\oplus$X’(W$\oplus$Z)} IG gate can be used to perform to perform logical operations like inverter, EX-OR, AND, EX-NOR and OR. It is a one- through gate which means one of the input variables is also the output. Its block diagram is shown in Figure 27 [74].

Figure 27. IG gate

3.3.11 MKG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, Y, (W’Z’$\oplus$X’)$\oplus$Y, (W’Z’$\oplus$X’)Y$\oplus$(WX$\oplus$Z)}. MKG gate is used to realize logical functions like NAND, NOT, NOR, EX-OR, AND, EX-NOR and OR. The MKG gate is categorized as a two-through gate, indicating that it has the distinct property of utilizing two of its input variables as outputs as well. Its block diagram is shown in Figure 28 [74].

Figure 28. MKG gate

Figure 29. BME gate

3.3.12 BME gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, WX$\oplus$Y, WZ$\oplus$Y, W’X$\oplus$Y$\oplus$Z}. The quantum cost is 5. Its block diagram is shown in Figure 29 [68].

3.3.13 PTR gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={(X$\oplus$Y)’, X$\oplus$Y$\oplus$Z, Z(X$\oplus$Y)+XY, X’(Y$\oplus$Z)=YZ}. Its block diagram is shown in Figure 30 [75].

Figure 30. PTR gate

3.3.14 PAO gate

The Peres And-Or Gate (PAOG) represents an extension of the Peres gate, specifically designed for ALU (Arithmetic Logic Unit) implementation. The input is expressed as In={V,W,X,Y,Z} and the output is expressed as Out={W, W$\oplus$X, WX$\oplus$Y, ((W$\oplus$X)$\oplus$Z)$\oplus$(WX$\oplus$Y)}. The PAOG can be configured with two select inputs, allowing it to execute four unique logical operations on its two output signals. These operations encompass OR, NOR, AND, and NAND. This versatile gate has a quantum cost of 6, and its block diagram is visually represented in Figure 31 [65].

Figure 31. PAOG gate

3.3.15 RC gate

The input vector of reversible comparator gate is In={W, X, Y, Z} and the output is represented as Out={W, W$\oplus$WX$\oplus$Y, X$\oplus$Y$\oplus$WX, W$\oplus$X$\oplus$Z}.The quantum cost is 5. Y and Z are the control lines when =0 and Z=1, it will compare W and X. Its block diagram is shown in Figure 32 [65].

Figure 32. RC gate

3.3.16 RC-II gate

RC-II gate is a reversible sign bit comparator. The input vector of Reversible comparator gate is In={W, X, Y, Z} and the output is represented as Out={W, W’X$\oplus$Z, W$\oplus$X$\oplus$Y, WX’$\oplus$Z}. RC-II gate is used to compare two unsigned bits. Its block diagram is shown in Figure 33 [66].

Figure 33. RC-II gate

3.3.17 HNG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, X, W$\oplus$X$\oplus$Y, (W$\oplus$X)Y$\oplus$(WX$\oplus$Z)}. The quantum cost of the HNG is 6. When Z=0, the circuit works as full adder. Its block diagram is shown in Figure 34 [65].

Figure 34. HNG gate

3.3.18 HCG gate

As outlined by James et al. [76], the Hamming Code Generating gate operates as a pass-through gate, wherein one of the input variables is simply mirrored as the output. Its block diagram is shown in Figure 35. The input is represented as In={W, X, Y, Z} and the output is represented as Out={X, W$\oplus$X$\oplus$Y, W$\oplus$X$\oplus$Z, W$\oplus$Y$\oplus$Z}. HCG is used to implement Hamming error coding and detection circuits [75].

Figure 35. HCG gate

3.3.19 FAS gate

The Full Adder Subtraction (FAS) gate is capable of executing both full addition and full subtraction operations. The input is represented as In={W, X, Y, Z} and the output is represented as Out={W$\oplus$X$\oplus$Y, (X$\oplus$Y$\oplus$Z)W$\oplus$(Y$\oplus$Z)X, Y, X$\oplus$Y$\oplus$Z}. Its quantum cost is 8. Its block diagram is shown in Figure 36 [75].

Figure 36. FAS gate

3.4 5×5 reversible logic gates

3.4.1 PPRG gate

Parity preserving reversible gate is the one through which means one of its inputs is also an output. It is a universal gate. The input is characterised as In={V, W, X, Y, Z} and the output is characterised as Out={V, (V’X’$\oplus$W’)$\oplus$Y, (V’X’$\oplus$W’)Y$\oplus$VW$\oplus$X, VW’$\oplus$X’$\oplus$(V’X’$\oplus$W’)’Y, (Y$\oplus$Z)$\oplus$VX}. P2RG gates can be singly used to build a full adder and full subtractor. Its block diagram is shown in Figure 37 [77].

Figure 37. PPRG gate

3.4.2 MG gate

Morrison gate is programmable reversible logic gate. The input is represented as In={V, W, X, Y, Z} and the output is represented as Out={V, V$\oplus$W, (V$\oplus$W)$\oplus$X,VW$\oplus$Y, ((V$\oplus$W)$\oplus$Z)$\oplus$(VW$\oplus$Y)}. The quantum cost of the MG is 7. Its block diagram is shown in Figure 38 [65].

Figure 38. MG gate

3.4.3 OD gate

The input is enumerated as In={V, W, X, Y, Z}, while the output is enumerated by Out={(W+X)$\oplus$Y$\oplus$V, W, X, Y, (W+X)Y$\oplus$Z$\oplus$VY}. Overflow Detection gate has a quantum cost of 10. OD gate is used for overflow detection. Its block diagram is shown in Figure 39 [75].

Figure 39. OD gate

3.4.4 NG-PP

The input is characterised as In={V, W, X, Y, Z} and the output is characterised as Out={V, W, X, V$\oplus$W$\oplus$X$\oplus$Y, V$\oplus$W$\oplus$X$\oplus$Z}. The NG-PP gate incurs a quantum cost of 5, as reported by Misra et al. [78]. It is used as a parity generator and parity checker circuit [79]. Its block diagram is shown in Figure 40.

Figure 40. NG-PP gate

3.4.5 HG-PP gate

The input is described as In={V, W, X, Y, Z} and the output is described as Out={V$\oplus$X$\oplus$Z, W$\oplus$X, X, Y$\oplus$Z, Z}. The quantum cost of the HG-PP gate is 4. The number of 1’s in input and output are the same. HG-PP gate is used to design the hamming code [78, 80]. Its block diagram is shown in Figure 41 [75].

Figure 41. HG-PP gate

3.5 6×6 reversible logic gates

3.5.1 BSCL gate

As per Rashmi et al. [81], the Binary Coded Decimal Subtraction Correction (BSCL) gate has a dual role. It can either compute correction logic for BCD subtraction or, based on the control signal, transmit the data directly to the output.The input is represented as In={U, V, W, X, Y, Z} and the output represented as Out={Z$\oplus$Y, Z’U+Z[Y’{U$\oplus$(V+W)}+Y{U+VWX}], Z’V+[Y(V$\oplus$W)+Y(V$\oplus$WX)], Z’W+ZY’W+ZY(W$\oplus$X), Z$\oplus$X, Z}. In this context, the control signal Z dictates the output behavior: when Z equals 0; U, V, W, X, and Y are directly transmitted to the output. However, if Z equals 1 and Y is 0, the output reflects the nine's complement of the input binary number represented by U, V, W, and X. Alternatively, if Y equals 1, the output results from adding the binary number 0001 to UVWX, providing a valid corrected subtraction outcome. Its block diagram is shown in Figure 42 [75].

Figure 42. BSCL gate

The application of reversible gates along with their quantum cost are tabulated in Table 1. The applications of some of the noteworthy reversible gates are mentioned below as well as Figure 43.

CNOT gate: CNOT gates are fundamental in creating entanglement, implementing quantum algorithms, and performing quantum error correction. CNOT gates are employed in quantum key distribution protocols. They contribute to secure communication by creating entangled states for secure key exchange between parties. In quantum teleportation protocols, CNOT gates are used to transfer the state of one quantum system to another, a process critical in quantum communication and quantum networking. Beyond Shor's and Grover's algorithms, CNOT gates are integral in various quantum algorithms, including quantum simulations, optimization problems, and quantum machine learning. CNOT gates are used in reversible logic synthesis, random number generation circuits, designing reversible circuits, and creating reversible arithmetic and data processing circuits [76, 82].

Toffoli gate (CCNOT gate): Toffoli gates play a key role in the design of quantum circuits for various applications. They are used in creating quantum adders, multicontrolled gates, and quantum carry-lookahead circuits. Toffoli gates, along with other gates, are vital in creating quantum superposition states. Superposition is a fundamental quantum property used in many quantum algorithms and quantum data representations.Toffoli gates are utilized in reversible computing to design complex reversible circuits, reversible logic synthesis, and reversible arithmetic circuits. They are also used in quantum algorithms, quantum error correction, and implementing various logic gates in quantum circuits [83, 84].

Fredkin gate (C-SWAP gate): Fredkin gates find applications in quantum permutation networks. These networks rearrange the order of quantum states, which is essential in quantum sorting algorithms and quantum data permutation tasks. The gates enable conditional swapping or routing of data in reversible data routing circuits and permutation networks. In quantum multiplexing, Fredkin gates are employed to combine and separate quantum states, a valuable process in quantum communication and networking. Fredkin gates find applications in reversible logic design, reversible arithmetic circuits, and reversible multiplexers [85-89].

Peres gate (Peres-Horodecki gate): Peres gates are used in quantum data compression techniques, facilitating the efficient storage and transmission of quantum information. Peres gates are used to detect and analyze entanglement in quantum systems. They play a role in entanglement verification protocols and quantum information processing [90-93]. In quantum key distribution, they are employed to generate secure encryption keys, which are essential for quantum secure communication. The gates contribute to quantum channel estimation, an important process in quantum communication and information transmission.

Feynman gate (Hadamard gate): Feynman gates, or Hadamard gates, create superposition and are employed in a wide range of quantum algorithms, including quantum search algorithms like Grover's algorithm [94-97].

Swap gate: Swap gates are used in quantum algorithms for reordering and swapping quantum states, such as in quantum sorting and quantum data permutation [98-100].

The research group at University of Florida designed four chips based on reversible computing. Frank published in reference [101] that cost-efficiency of irreversible computing may have hit a theromodynamic wall, whereas for reversible computing it can continue to improve [102]. These are just a few examples of the applications of different reversible gates. Each gate has its own unique functionality and can be utilized in various contexts, depending on the specific requirements of the computation or algorithm.

Table 1. Reversible logic gates summary

Figure 43. Comparison of quantum cost of reversible logic gates

This comprehensive review paper serves as a meticulous exploration of reversible logic gates, taking into consideration over 50 distinct gate types, with prominent examples like the CNOT, Toffoli, and Fredkin gates. The paper's primary focus is to underscore the significant advantages associated with reversible logic, which encompasses a substantial reduction in power consumption, the pivotal aspect of information reversibility, and the notable decrease in heat generation during computation.

The applications of reversible logic gates are profoundly diverse and span a spectrum of domains. In quantum computing, these gates hold a fundamental role in the implementation of quantum algorithms and in preserving quantum coherence during operations. In the arena of low-power circuit design, where energy efficiency is a critical consideration, reversible gates have shown significant promise. They have been effectively harnessed in reversible arithmetic circuits, memory system design, and the development of error correction techniques, leading to reduced power consumption and an overall enhancement in circuit performance.

Furthermore, the exploration of reversible gates extends its reach into the field of nanotechnology. It opens avenues for the potential advancement of molecular computing, which could lead to substantial progress in miniaturized computing systems, marking a significant development in the realm of information technology.

Looking into the future, the field of reversible logic gates presents a host of opportunities for further research and innovation. These opportunities are closely tied to the field's ongoing challenges, including the design and optimization of larger reversible circuits, the development of efficient synthesis methodologies, and the exploration of new architectures and technologies that can effectively tackle the practical hurdles associated with implementation. Research in these directions promises to significantly advance the field's boundaries.

The implications arising from this review are of practical importance. Reversible logic gates are positioned to contribute substantially to energy-efficient low-power circuit design, thereby extending the life of battery-powered electronic devices and promoting sustainable energy practices. Additionally, they have the potential to strengthen the security and performance of quantum computing, which is of paramount significance in the age of data security and quantum technological advancements. Beyond these applications, reversible gates have the capacity to revolutionize the field of nanotechnology, presenting avenues for molecular computing that could lead to the development of more compact and efficient computing systems.

It is imperative to acknowledge the inherent limitations of this study. While it provides a comprehensive overview of the field, it does not delve into specific technical details. Moreover, the nature of quantum computing and its related fields is highly dynamic and continuously evolving, which means that the observations and analyses contained in this review are reflective of a specific point in time.

In summary, this review functions as a meticulously constructed map of the intricate world of reversible logic gates, highlighting their remarkable advantages and multifaceted applications. The paper’s discussion of future research directions underscores the promising outlook for the field and underscores the practical implications, which could redefine the domains of low-power circuit design, quantum computing, and nanotechnology.

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Materials Horizons

Recent advances in flexible memristors for advanced computing and sensing.

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a School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore, Singapore E-mail: [email protected] , [email protected]

Conventional computing systems based on von Neumann architecture face challenges such as high power consumption and limited data processing capability. Improving device performance via scaling guided by Moore's Law becomes increasingly difficult. Emerging memristors can provide a promising solution for achieving high-performance computing systems with low power consumption. In particular, the development of flexible memristors is an important topic for wearable electronics, which can lead to intelligent systems in daily life with high computing capacity and efficiency. Here, recent advances in flexible memristors are reviewed, from operating mechanisms and typical materials to representative applications. Potential directions and challenges for future study in this area are also discussed.

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J. Xu, Z. Luo, L. Chen, X. Zhou, H. Zhang, Y. Zheng and L. Wei, Mater. Horiz. , 2024, Advance Article , DOI: 10.1039/D4MH00291A

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Why Are Companies That Lose Money Still So Successful?

• Vijay Govindarajan,
• Shivaram Rajgopal,
• Anup Srivastava,
• Aneel Iqbal,
• Elnaz Basirian

New research on how to identify investments that produce delayed but real profits — not just those that produce short-term accounting profits.

In a well-functioning capital market, profits should be the sole criterion for firm survival; that is, firms reporting losses should disappear. Of late, however, loss-making firms are highly sought after by investors — often more than some profitable firms. Unicorns, or startups with valuations exceeding a billion dollars, are examples of such loss-making firms. What has changed over time? When and why did losses lose their meaning? The authors’ series of new research papers provide some answers, guiding managers to make the right investments: those that produce delayed but real profits — not just those that produce short-term accounting profits but decimate shareholder wealth in long run.

In 1979, psychologists Daniel Kahneman and Amos Tversky famously posited that losses loom larger than gains in human decision-making. For example, a dollar of loss affects our behavior more than a dollar of profits . Likewise, when a firm announces losses, its stock price declines more dramatically than it increases for the same dollar amount of profits. Investors abandon and lenders tend to stop financing loss-making firms , which then start restructuring their business lines and laying off employees. Some firms go even further, conducting M&A transactions without substance and “managing earnings” to report profits instead of a loss.

• Vijay Govindarajan is the Coxe Distinguished Professor at Dartmouth College’s Tuck School of Business, an executive fellow at Harvard Business School, and faculty partner at the Silicon Valley incubator Mach 49. He is a New York Times and Wall Street Journal bestselling author. His latest book is Fusion Strategy: How Real-Time Data and AI Will Power the Industrial Future . His Harvard Business Review articles “ Engineering Reverse Innovations ” and “ Stop the Innovation Wars ” won McKinsey Awards for best article published in HBR. His HBR articles “ How GE Is Disrupting Itself ” and “ The CEO’s Role in Business Model Reinvention ” are HBR all-time top-50 bestsellers. Follow him on LinkedIn . vgovindarajan
• Shivaram Rajgopal is the Roy Bernard Kester and T.W. Byrnes Professor of Accounting and Auditing and Vice Dean of Research at Columbia Business School. His research examines financial reporting and executive compensation issues and he is widely published in both accounting and finance.
• Anup Srivastava holds Canada Research Chair in Accounting, Decision Making, and Capital Markets and is a full professor at Haskayne School of Business, University of Calgary. In a series of HBR articles, he examines the management implications of digital disruption. He specializes in the valuation and financial reporting challenges of digital companies. Follow Anup on  LinkedIn .
• Aneel Iqbal is an assistant professor at Thunderbird School of Global Management, Arizona State University. He examines the accounting measurement and financial disclosures for new-economy firms and incorporates his wide-ranging industry experience into his research and teaching. He is a seasoned accounting and finance professional with diverse experience in auditing, financial analysis, business advisory, performance management, and executive training. Follow Aneel on LinkedIn .
• Elnaz Basirian is a PhD student at the Haskayne School of Business. She examines the influence and role of intangibles in accounting and finance, aimed at improving valuation and market efficiency. She brings a decade of work experience in international financial markets. Follow Elnaz on LinkedIn .

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Research with integrity – GenAi, paper mills and inclusivity

27 June 2024

As the global research integrity community came together for the 8 th World Conference on Research Integrity, we asked: what are the big issues and what can we do to tackle them? Andrew Porter and the team give us the low-down from the front line of research integrity…

Climbing one of the hills near the Acropolis on the first evening of the 8 th World Conference on Research Integrity (WCRI) , I was treated to a wonderful view of Athens. Having taken the Metro from the airport, I’d only seen Athens at street level, but here it was… the whole city spread out.

This fresh perspective – seeing the big picture – made me think about the opportunities a conference like this offers to do the same. The space it can afford to think about what makes research tick, the different roles and activities supporting good research, and some of the bad practices affecting the quality of science.

The field of metascience, or research on research, is rapidly growing, evidenced by many presentations at this year’s conference about how to measure research integrity.

It may strike you as unusual that there are conferences on research integrity, but over the years it has become an active area of research in its own right. The field of metascience, or research on research, is rapidly growing, evidenced by many presentations at this year’s conference about how to measure research integrity. How can we know if a new training actually works? What data do we have on equality and diversity that could help us understand whose voices are not being heard in research, academia and publishing? How many publications contain fabricated, falsified or plagiarised data?

These and many other questions were discussed over 4 days in sessions ranging from the philosophical to the highly specific and practical.

The conferences began as a joint U.S. – European venture , expanding from a relatively small meeting in 2007 in Lisbon to this gathering of 800 attendees.  Along the way the conferences have produced various statements – co-created by attendees – which have helped shape research practices worldwide.  These include the 2010 Singapore Statement , which set out a values-based definition of research integrity, and forms the basis for the UK Concordat to Support Research Integrity and the recent Cape Town Statement on fairness, equity and diversity in research. For more on the WCRI, see Catherine’s earlier blog .

Intelligent approaches to Gen AI

Some of the big areas covered at the conference included paper mills and fake clinical trials ; the implications of generative AI; and equity, diversity and inclusion.  It’s clear, however, these aspects are deeply interwoven.

For instance, generative AI tools (many of which are now embedded in commercial software such as Photoshop 24 ) can be used to create fake text and data for paper mills, but might also help screen for fraudulent activity, support researchers writing in English as a second language, and require good training and education for ethical use.

Much of the conversation around gen AI is focussed on creating guidelines that are flexible and values-based; the field is moving so fast that making them too specific risks guidance going out of date. Addressing gen AI through the lens of existing research integrity structures however makes for more generalisable support, as discussed previously .

Fake it ‘till you break it…

Paper mills were a recurring theme across many different topic areas. I came away with a strong sense that we need to raise awareness amongst researchers – there is a real risk that fake research is polluting the literature.

Paper mills produce fake research publications for profit. Whole networks exist purely to sell authorship online, creating fake data and text, using fake email addresses and creating fake academics – even taking over the whole editorial and peer review process to completely bypass scrutiny. It’s a shocking concept, but   evidence of the scale of the problem keeps accumulating. For instance, over 8000 papers were retracted last year from Hindawi journals , a subsidiary of Wiley, primarily due to paper mill activity.

The pollution of scientific literature by fake studies leads to miscalculation of the size and importance of whole fields of research, meaning we can come to wrong conclusions on safety and efficacy

However, the research integrity community is stepping up to counter this. Sleuths, like Elisabeth Bik and Jana Christopher , work to detect these activities, along with academics developing tools to screen publications, such as Jack Wilkinson from the University of Manchester who presented the INSPECT-SR tool aimed at weeding out fake clinical trials.

Research integrity teams at publishers try to verify authorship, screen papers , obtain raw data, and use tools like iThenticate to spot plagiarism and image alteration . However, those wily paper mills will often submit manuscripts to multiple journals at the same time, and so the Committee on Publication Ethics (COPE) and STM , the trade body for academic publishers, are working on ways for publishers to spot these multiple submissions .

But this is, clearly, not just harmless cat-and-mouse antics. The very real dangers of this fraudulent activity were brought home in a number of sessions. One speaker reported raising concerns about more than 900 articles related to studies about women’s health, and while this has led to 151 retractions and 75 expressions of concern, a large volume of problematic literature persists – and it can take an average of 3 years for journals to address concerns.

The pollution of scientific literature by fake studies leads to miscalculation of the size and importance of whole fields of research, meaning we can come to wrong conclusions on safety and efficacy, even from systematic reviews (the gold standard for evidence-based medicine, influencing medical practice and government decision-making processes), and drive researchers down wasteful and frustrating dead ends.

Solution suggestions

How to address these problems? Suggestions included more people screening for issues already in the literature (like Jennifer Byrne whose team recently identified fake cell lines entering the literature), more research on the scale of the problem ( such as from the new voluntary body United2Act ), awareness raising for researchers and editors, and pre-screening manuscripts and verifying authenticity of data at an institutional level.

Attendees also advocated for deeper reform of academic publishing and reward models, for slower science (and the publication of fewer papers) and to move away from researchers being judged primarily on the number and type of papers they publish – something many institutions and funders have signed up to, but which still persists in research culture.

Some suggestions to address fraud – such requiring authors to have academic email addresses – could have unintended consequences, as researchers in low- and middle-income countries are often not provided with these. This reflected the ‘world’ part of the conference; funds are provided to support attendance from low- and middle-income countries, and it was encouraging to hear a diverse range of perspectives. A strong case was made that bringing in under-represented voices, making research truly global, representative and fair, is important for all those involved in research.

If we were to zoom out of the specific details of the conference, and try to get an overview, it might look something like: Bring in, Build up, and Keep out.

Bring in diverse and previously excluded voices. Build up good research practices, including for those researchers who are trying their best to act with integrity. Keep out fraudulent research, disinformation and fake data.

This framing might help us determine which kinds of initiatives, driven by which parts of the research community, are most effective and impactful for supporting integrity. WCRI has shown us much of what we have to do, and we have a decent map of the routes. The next step is to get back down to street level and implement some of them.

Take-home thoughts

Several CRUK research professionals attended WCRI – here’s what they think you should know…

Catherine Winchester, Head of the Research Integrity Service at the CRUK Scotland Institute

“It was clear that whatever role we have in a research organisation, we all have a part to play in collectively improving research quality and reproducibility, and that research integrity advisers are key partners in this endeavour. “Plan – do – act – check”, the take home message from Anja Gilis, director of preclinical quality planning and strategy at Johnson & Johnson, struck a chord with me and epitomises the iterative approach we have been implementing at the CRUK Scotland Institute.

One ‘doing’ initiative I learned about at the conference is the RoSiE project to foster reproducible open science in Europe, which is developing guidelines and training materials on open and FAIR science. And falling under ‘checking’, benchmarking surveys on culture, research integrity barriers and incentives were a popular theme at the conference. Looking forward it will be interesting to see how their information is used to act to change behaviour and practices. Indeed, the UK Committee on Research Integrity has undertaken a project to explore indicators of research integrity , which was presented by Jane Alfred.”

Sue Russell, Senior Policy and Governance Manager at CRUK

“It always pays to see what resources already exist to help you achieve your integrity goals. For example, we learned about SOPs4RI which helps research organisations and funders develop their own Research Integrity Promotion Plans.

How funders can then translate these into adaptive funding policies and help embed into broader practices will be important. Noesk’s Strategy for Culture Change – shared more than once at WCRI – was useful reminder of the foundations and levels needed.

But it will take collective, cross-sector collaboration – researchers, research integrity teams, research organisations, publishers, sector bodies, and funders coming together – to discuss and resolve issues. Great examples of fruitful collaborations were showcased at the conference from Only Good Antibodies to improve biomedical research and CRUK’s own Registered Reports Funding Partnership pilot – our consortium between us a funder, research organisation and publishers working together to improve research quality.

Our Research Integrity Advisors at CRUK Institutes have built very strong foundations – both within their institutions and more broadly – on this culture change journey, which WCRI made me appreciate even more.”

All sessions of the 8 th World Conference on Research Integrity were recorded, and recordings will be made publicly available 2 months after the conference.

Check out some of the posters presented by the CRUK integrity team at the 8th World Conference on Research Integrity

Dr andrew porter.

Andrew is Research Integrity and Training Adviser at Cancer Research UK Manchester Institute

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